ISL12032IVZ-T Intersil, ISL12032IVZ-T Datasheet - Page 15

• Manufacturer Part Number: ISL12032IVZ-T
• Description: IC RTC LP BATT BACK SRAM 14TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12032IVZ-T

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12032IVZ-TTR

Event Count (EVTCNT)
The EVTCNT register increments automatically each time an
event occurs. The register is set to 00h on initial power-up.
The maximum count is 255, and will stay at that value until
set to zero via an I
Performing a write of 00h to this register will clear the
contents of this register and all levels of the TSEVT section.
A clear to this register should be done with care. Write event
index register zero only selects first event time stamp. Write
event count EVNTCNT zero will both clear event counter
and all time stamps.
Control Registers
Addresses [0Ch to 14h]
The control registers (INT, FO, EVIC, EVIX, TRICK,
PWRVDD, PWRBAT, AC, and FTR) contain all the bits
necessary to control the parametric functions on the
ISL12032.
Interrupt Control Register (INT)
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM0,
ALM1, LVDD, LBAT85, and LBAT75 status bits only. When
ARST bit is set to “1”, these status bits are reset to “0” after a
valid read of the SRDC Register (with a valid STOP
condition). When the ARST is cleared to “0”, the user must
manually reset the ALM0, ALM1, LVDD, LBAT85, and
LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Register section. The factory default setting of this bit is
“0”. Upon initialization or power-up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle. This bit will remain set until reset to “0” or a
complete power-down occurs (V
ALARM INTERRUPT MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarms will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ pin when the RTC is triggered
by either alarm as defined by the Alarm0 section (1Dh to
ADDR
ADDR
0Bh
0Ch
TABLE 6. INTERRUPT CONTROL REGISTER (INT)
TABLE 5. EVENT COUNTER REGISTER (EVTCNT)
EVC7 EVC6 EVC5 EVC4 EVC3 EVC2 EVC1 EVC0
ARST WRTC
7
7
6
2
6
C write.
5
IM
5
15
4
DD
4
X
= VBAT = 0.0V)
3
X
3
X
2
2
ALE1 ALE0
1
1
0
0
ISL12032
22h) or the Alarm1 section (23h to 28h). When the IM bit is
cleared to “0”, the alarm will operate in standard mode,
where the IRQ pin will be set LOW until both the
ALM0/ALM1 status bits are cleared to “0”.
ALARM 1 (ALE 1)
This bit enables the Alarm1 function. When ALE1 = “1”, a
match of the RTC section with the Alarm1 section will result
is setting the ALM1 status bit to “1” and the IRQ output LOW.
When set to “0”, the Alarm1 function is disabled.
ALARM 0 (ALE 0)
This bit enables the Alarm0 function. When ALE0 = 1, a
match of the RTC section with the Alarm1 section will result
is setting the ALM0 status bit to “1” and the IRQ output LOW.
When set to “0”, the Alarm0 function is disabled.
Frequency Out Register (FO)
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables F
(i.e. VBAT power source active). When the FOBATB is set to
“1” the F
the FOBATB is cleared to “0”, the F
battery backup mode (default). Note that F
output and needs no pull-up resistor. Note also that battery
current drain will be higher with F
backup mode.
FREQUENCY OUT CONTROL BITS (FO <2:0>)
These bits enable/disable the frequency output function and
select the output frequency at the F
frequency selection. Note that frequencies from 4096Hz to
32768Hz are derived from the Crystal Oscillator, and the 1.0,
10, and 50/60Hz frequencies are derived from the AC clock
input. The exception to this is when the AC input qualification
has failed, and the crystal oscillator is used for the 1.0Hz
F
ADDR
OUT
0Dh
FREQUENCY,
.
32768
16372
TABLE 8. FREQUENCY SELECTION OF F
F
50/60
8192
4096
High
Low
OUT
OUT
TABLE 7. FREQUENCY OUT REGISTER (FO)
1
X
7
pin is disabled during battery backup mode. When
X
6
UNITS
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
X
5
OUT
FOBATB
during battery backup mode
OUT
FO2
0
0
0
0
1
1
1
1
4
OUT
OUT
enabled in battery
pin is enabled during
pin. See Table 8 for
OUT
X
3
FO1
0
0
1
1
0
0
1
1
FO2 FO1 FO0
is a CMOS
2
OUT
April 16, 2009
PIN
1
FN6618.2
FO0
0
1
0
1
0
1
0
1
0