DP8572AN National Semiconductor, DP8572AN Datasheet - Page 3

IC REAL TIME CLOCK W/RAM 24 DIP

DP8572AN

Manufacturer Part Number
DP8572AN
Description
IC REAL TIME CLOCK W/RAM 24 DIP
Manufacturer
National Semiconductor
Type
Clock/Calendar/NVSRAMr
Datasheet

Specifications of DP8572AN

Memory Size
44B
Time Format
HH:MM:SS:hh (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP8572AN
DP8572

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Company
Part Number
Manufacturer
Quantity
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Part Number:
DP8572AN
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DP8572AN
Manufacturer:
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Quantity:
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READ TIMING
WRITE TIMING
INTERRUPT TIMING
8572A
AC Electrical Characteristics
V
Note 8 Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low Hence read commences when
both signals are low and terminates when either signal returns high
Note 9 Hold time is guaranteed by design but not production tested This limit is not used to calculate outgoing quality levels
Note 10 Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low Hence write commences when
both signals are low and terminates when either signal returns high
AC Test Conditions
Note 11 C
Note 12 S1
Capacitance
Note 13 This parameter is not 100% tested
Note 14 Output rise and fall times 25 ns max (10%–90%) with 100 pF load
CC
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
C
C
AR
RW
CD
RAH
RD
DZ
RCH
DS
AW
WAH
CW
WW
DW
WDH
WCH
ROLL
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 12)
IN
OUT
e
S1
S1
5V
L
e
e
e
e
g
GND for active high to high impedance measurements
open for all other timing measurements
100 pF includes jig and scope capacitance
V
10% V
CC
Input Capacitance
Output Capacitance
for active low to high impedance measurements
Parameter
BB
Address Valid Prior to Read Strobe
Read Strobe Width (Note 8)
Chip Select to Data Valid Time
Address Hold after Read (Note 9)
Read Strobe to Valid Data
Read or Chip Select to TRI-STATE
Chip Select Hold after Read Strobe
Minimum Inactive Time between Read or Write Accesses
Address Valid before Write Strobe
Address Hold after Write Strobe (Note 9)
Chip Select to End of Write Strobe
Write Strobe Width (Note 10)
Data Valid to End of Write Strobe
Data Hold after Write Strobe (Note 9)
Chip Select Hold after Write Strobe
Clock Rollover to INTR Out is Typically 16 5 s
(Note 13)
(T
A
e
e
3V V
25 C f
PFAIL l
e
Active High
Active Low
6 ns (10%–90%)
1 MHz)
GND to 3 0V
V
Typ
IH
5
7
Parameter
1 3V
C
L
b
a
e
0 5V
0 5V
Units
100 pF (unless otherwise specified)
pF
pF
3
Min
20
80
50
20
90
80
50
3
0
3
3
0
Max
80
70
60
TL F 9980 – 2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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