AD7328BRUZ Analog Devices Inc, AD7328BRUZ Datasheet - Page 15

• Manufacturer Part Number: AD7328BRUZ
• Description: IC ADC 12BIT+ SAR 8CHAN 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7328BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Using AD7328 in Appls with Single-Ended Industrial-Level Signals (CN0047)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 30mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 13bit
• Sampling Rate: 1MSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Supply Current: 900µA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7328CBZ - BOARD EVALUATION FOR AD7328
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7328 is a fast, 8-channel, 12-bit plus sign, bipolar input,
serial ADC. The AD7328 can accept bipolar input ranges that
include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to +10 V
unipolar input range. A different analog input range can be
programmed on each analog input channel via the on-chip
registers. The AD7328 has a high speed serial interface that
can operate at throughput rates up to 1 MSPS.
The AD7328 requires V
voltage analog input structures. These supplies must be equal
to or greater than the analog input range. See Table 6 for the
requirements of these supplies for each analog input range. The
AD7328 requires a low voltage 2.7 V to 5.25 V V
power the ADC core.
Table 6. Reference and Supply Requirements for Each
Analog Input Range
Selected Analog
Input Range (V)
±10
±5
±2.5
0 to +10
To meet the performance specifications when the AD7328 is
configured with the minimum V
analog input range, the throughput rate should be decreased from
the maximum throughput range (see the Typical Performance
Characteristics section). Figure 18 and Figure 19 show the change
in INL and DNL as the V
operating at the maximum throughput rate, as the V
supply voltages are reduced, the INL and DNL error increases.
However, as the throughput rate is reduced with the minimum
V
Figure 31 shows the change in THD as the V
are reduced. At the maximum throughput rate, the THD degrades
significantly as V
reduce the throughput rate when using minimum V
supplies so that there is less degradation of THD and the specified
performance can be maintained. The degradation is due to an
increase in the on resistance of the input multiplexer when the
V
DD
DD
and V
and V
SS
SS
supplies, the INL and DNL error is reduced.
supplies are reduced.
DD
and V
Reference
Voltage (V)
2.5
3.0
2.5
3.0
2.5
3.0
2.5
3.0
DD
SS
DD
are reduced. It is therefore necessary to
and V
and V
DD
SS
Full-Scale
Input
Range (V)
±10
±12
±5
±6
±2.5
±3
0 to +10
0 to +12
and V
SS
dual supplies for the high
voltages are varied. When
SS
supplies for a chosen
DD
V
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
CC
and V
CC
(V)
supply to
DD
DD
SS
Minimum
V
±10
±12
±5
±6
±5
±5
+10/AGND
+12/AGND
and V
and V
supplies
DD
/V
SS
Rev. B | Page 15 of 36
SS
(V)
SS
The analog inputs can be configured as eight single-ended inputs,
four true differential input pairs, four pseudo differential inputs,
or seven pseudo differential inputs. Selection can be made by
programming the mode bits, Mode 0 and Mode 1, in the control
register.
The serial clock input accesses data from the part and provides the
clock source for the successive approximation ADC. The AD7328
has an on-chip 2.5 V reference. However, the AD7328 can also
work with an external reference. On power-up, the external
reference operation is the default option. If the internal reference
is preferable, the user must write to the reference bit in the
control register to select the internal reference operation.
The AD7328 also features power-down options to allow power
savings between conversions. The power-down modes are selected
by programming the on-chip control register as described in the
Modes of Operation section.
CONVERTER OPERATION
The AD7328 is a successive approximation analog-to-digital
converter built around two capacitive DACs. Figure 23 and
Figure 24 show simplified schematics of the ADC in single-
ended mode during the acquisition and conversion phases,
respectively. Figure 25 and Figure 26 show simplified schematics
of the ADC in differential mode during acquisition and conversion
phases, respectively.
The ADC is composed of control logic, a SAR, and capacitive
DACs. In Figure 23 (the acquisition phase), SW2 is closed and
SW1 is in Position A, the comparator is held in a balanced con-
dition, and the sampling capacitor array acquires the signal on
the input.
When the ADC starts a conversion (see Figure 24), SW2 opens and
SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the capacitive DAC to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
Figure 23. ADC Configuration During Acquisition Phase, Single-Ended Mode
V
IN
0
AGND
B
A
SW1
C
S
SW2
COMPARATOR
CAPACITIVE
CONTROL
LOGIC
DAC
AD7328