AD7328BRUZ Analog Devices Inc, AD7328BRUZ Datasheet - Page 17

• Manufacturer Part Number: AD7328BRUZ
• Description: IC ADC 12BIT+ SAR 8CHAN 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7328BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Using AD7328 in Appls with Single-Ended Industrial-Level Signals (CN0047)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 30mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 13bit
• Sampling Rate: 1MSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Supply Current: 900µA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7328CBZ - BOARD EVALUATION FOR AD7328
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Care should be taken to ensure that the analog input does
not exceed the V
Exceeding this value causes the diodes to become forward
biased and to start conducting into either the V
or the V
without causing irreversible damage to the part.
In Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
Track-and-Hold Section
The track-and-hold on the analog input of the AD7328 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the track-
and-hold is greater than the Nyquist rate of the ADC. The AD7328
can handle frequencies up to 22 MHz.
The track-and-hold enters its tracking mode on the 14
rising edge after the CS falling edge. The time required to acquire
an input signal depends on how quickly the sampling capacitor
is charged. With zero source impedance, 305 ns is sufficient to
acquire the signal to the 13-bit level. The acquisition time for
the ±10 V, ±5 V, and 0 V to +10 V ranges to settle to within
±½ LSB is typically 200 ns.
The acquisition time required is calculated using the following
formula:
where C is the sampling capacitance, and R is the resistance
seen by the track-and-hold amplifier looking at the input.
For the AD7328, the value of R includes the on resistance of the
input multiplexer and is typically 300 Ω. R
any extra source impedance on the analog input.
t
ACQ
Figure 30. Equivalent Analog Input Circuit, Differential Mode
SS
= 10 × ((R
supply rail. These diodes can conduct up to 10 mA
V
V
IN
IN
+
–
DD
SOURCE
and V
C1
C1
+ R) C)
SS
V
V
V
V
DD
DD
SS
SS
supply rails by more than 300 mV.
D
D
D
D
SOURCE
R1
R1
should include
DD
C2
C2
supply rail
th
SCLK
Rev. B | Page 17 of 36
The AD7328 enters track mode on the 14
When the AD7328 is run at a throughput rate of 1 MSPS with a
20 MHz SCLK signal, the ADC has approximately
to acquire the analog input signal. The ADC goes back into
hold mode on the CS falling edge.
As the V
the input multiplexer increases. Therefore, based on the equation
for t
to the AD7328 and, hence, decrease the overall throughput rate.
Figure 31 shows that if the throughput rate is reduced when
operating with minimum V
THD performance is maintained.
Unlike other bipolar ADCs, the AD7328 does not have a
resistive analog input structure. On the AD7328, the bipolar
analog signal is sampled directly onto the sampling capacitor.
This gives the AD7328 high analog input impedance. The
analog input impedance can be calculated from the following
formula:
where f
capacitor value.
C
Specifications section). When operating at 1 MSPS, the analog
input impedance is typically 75 kΩ for the ±10 V range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases, the
current required to drive the analog input therefore decreases.
Figure 31. THD vs. ±V
S
depends on the analog input range chosen (see the
ACQ
1.5 SCLK + t
Z = 1/(f
, it is necessary to increase the acquisition time provided
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
S
DD
is the sampling frequency, and C
5
/V
1MSPS
S
SS
× C
supply voltage is reduced, the on resistance of
7
S
8
DD
)
+ t
750kSPS
/V
SS
QUIET
Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS
9
±V
DD
DD
/V
11
and V
SS
SUPPLIES (V)
SS
13
supplies, the specified
V
INTERNAL REFERENCE
T
F
±5V RANGE
SE MODE
A
IN
CC
S
th
= 25°C
= 10kHz
is the sampling
= V
SCLK rising edge.
15
DRIVE
500kSPS
= 5V
17
AD7328
1
9