MAX1446EHJ+ Maxim Integrated Products, MAX1446EHJ+ Datasheet - Page 11

• Manufacturer Part Number: MAX1446EHJ+
• Description: IC ADC 10BIT 60MSPS 32-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1446EHJ+

• Number Of Bits: 10
• Sampling Rate (per Second): 60M
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Conversion Rate: 60 MSPs
• Resolution: 10 bit
• Snr: 59.5 dB
• Voltage Reference: 2.048 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 1495.3 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX1446 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Each sample moves through a pipeline stage
every half-clock cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated until the signal has been process-
ed by all 10 stages. Each stage provides a 1-bit resolu-
tion. Digital error correction compensates for ADC
comparator offsets in each pipeline stage and ensures
no missing codes.
Figure 2 displays a simplified functional diagram of the
input T/H circuit in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
are closed. The fully differential circuit samples the
input signal onto the two capacitors (C2a and C2b).
S2a and S2b set the common mode for the amplifier
Figure 1. Pipelined Architecture—Stage Blocks
V
IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED)
IN
V
IN
= INPUT VOLTAGE BETWEEN
V
IN
FLASH
ADC
1.5 bits
STAGE 1
T/H
______________________________________________________________________________________
Input Track-and-Hold Circuit
DAC
MDAC
Detailed Description
DIGITAL CORRECTION LOGIC
Σ
STAGE 2
D9–D0
10
x2
10-Bit, 60Msps, 3.0V, Low-Power
V
OUT
STAGE 10
ADC with Internal Reference
input. The resulting differential voltage is held on C2a
and C2b. S4a, S4b, S5a, S5b, S1, S2a, and S2b are
then opened before S3a, S3b and S4c are closed, con-
necting capacitors C1a and C1b to the amplifier output,
and S4c is closed. This charges C1a and C1b to the
same values originally held on C2a and C2b. This value
is then presented to the first stage quantizer and iso-
lates the pipeline from the fast-changing input. The
wide-input-bandwidth T/H amplifier allows the
MAX1446 to track and sample/hold analog inputs of
high frequencies beyond Nyquist. The analog inputs
(IN+ and IN-) can be driven either differentially or single
ended. It is recommended to match the impedance of
IN+ and IN- and set the common-mode voltage to mid-
supply (V
The MAX1446 full-scale range is determined by the
internally generated voltage difference between REFP
(V
ADC’s full-scale range is user adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (V
are internally buffered, low-impedance outputs.
Figure 2. Internal T/H Circuit
Analog Input and Reference Configuration
DD
IN+
IN-
/2 + V
TRACK
DD
S4a
S4b
HOLD
REFIN
/2) for optimum performance.
S4c
/4) and REFN (V
TRACK
HOLD
C2a
C2b
CLK
INTERNAL
S2a
INTERNAL
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
BIAS
BIAS
S1
S2b
DD
/2 - V
C1a
C1b
DD
COM
COM
/2), and REFN
S5a
S5b
REFIN
S3a
S3b
/4). The
OUT
OUT
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