LTC2442IG#PBF Linear Technology, LTC2442IG#PBF Datasheet - Page 21

• Manufacturer Part Number: LTC2442IG#PBF
• Description: IC ADC 24BIT 4CH 36-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2442IG#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 8k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 50mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Internal Serial Clock, 3-Wire I/O, Continuous
Conversion
This timing mode uses a 3-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 9. CS may be permanently tied to ground, simplifying
the user interface or isolation barrier. The internal serial
clock mode is selected by tying EXT HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW
(EOC = 0) indicating the conversion has fi nished and the
APPLICATIO S I FOR ATIO
BUSY
SDO
SCK
SDI
CS
DON'T CARE
CONVERSION
U
U
BIT 31
EOC
1
1
BIT 30
SLEEP
“0”
2
0
0.1V TO V
REFERENCE
W
Figure 9. Internal Serial Clock, Continuous Operation
ANALOG
BIT 29
INPUTS
VOLTAGE
SIG
EN
0.1µF
0.1µF
3
1µF
4.5V TO 5.5V
CC
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
MSB
SGL
4
29
30
31
28
12
13
11
17
18
10
6
7
8
9
ODD
V
REF
REF
CH0
CH1
CH2
CH3
COM
OUTA
–INA
ADCINA
OUTB
–INB
ADCINB
U
5
CC
+
–
LTC2442
MUXOUTA
MUXOUTB
0
6
BUSY
+INA
+INB
SDO
GND
SCK
EXT
SDI
CS
V
F
V
7
0
O
+
–
DATA OUTPUT
V
21
27
25
26
19
24
4, 5, 32
CC
device has entered the sleep state. The part remains in
the sleep state a minimum amount of time (≈500ns) then
immediately begins outputting data. The data output cycle
begins on the fi rst rising edge of SCK and ends after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the fi rst rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
33
36
35
34
3
1
2
TO 15V
A0
8
–15V TO GND
1µF
V
CC
OSR3
3-WIRE
SPI INTERFACE
9
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
OSR2
10
OSR1
11
BIT 20 BIT 19
OSR0 TWOX
12
13
14
BIT 0
DON'T CARE
15
LTC2442
32
2442 F09
CONVERSION
21
2442f