LTC1274CSW Linear Technology, LTC1274CSW Datasheet - Page 17

• Manufacturer Part Number: LTC1274CSW
• Description: IC A/D CONV 12BIT W/SHTDN 24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1274CSW

• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 20mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC1274CS

The narrow logic pulse on CONVST ensures that CONVST
doesn’t return high during the conversion (see Note 13
following the Timing Characteristics table).
In Mode 2 (Figure 15) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
both are in three-state until read by the MPU with the RD
signal. Mode 2 can be used for operation with a shared
MPU databus.
In slow memory and ROM modes (Figures 16 and 17) CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
A
PPLICATI
HBEN (LTC1277)
LTC1274 DATA
LTC1277 DATA
CS = RD = 0
CONVST
BUSY
O
CONVST
SLEEP
U
Figure 12. Internal Logic for Control Inputs CS, RD, CONVST, NAP and SLEEP (LTC1277)
NAP
RD
CS
S
Figure 13. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
DB11 TO DB0
(CONVST =
DATA (N – 1)
DATA (N – 1)
DB7 TO DB0
I FOR ATIO
U
t
(SAMPLE N)
5
t
4
t
CONV
W
t
6
DB7 TO DB0
)
U
DATA N
t
t
15
7
D
CLEAR
DB11 TO DB8
FLOP
DB11 TO DB0
FLIP
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low,
forcing the processor into a Wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high releasing the
processor; the processor applies a logic high to RD
(= CONVST) and reads the new conversion data.
In ROM mode the processor applies a logic low to RD
(= CONVST), starting a conversion and reading the
previous conversion result. After the conversion is com-
plete, the processor can read the new result and initiate
another conversion.
DATA N
DATA N
t
Q
16
BUSY
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
DB11....DB0
(SAMPLE N + 1)
CONVERSION
START (RISING
EDGE TRIGGER)
DB7 TO DB0
DATA N
1274/77 • F12
LTC1274/LTC1277
DATA (N + 1)
DB7 TO DB0
DB11 TO DB0
DATA (N + 1)
LTC1274/77 • F13
17