MAX1183ECM+TD Maxim Integrated Products, MAX1183ECM+TD Datasheet - Page 11

• Manufacturer Part Number: MAX1183ECM+TD
• Description: IC ADC 10BIT 40MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1183ECM+TD

• Number Of Bits: 10
• Sampling Rate (per Second): 40M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 180mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track-and-hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switch-
es S3a and S3b connect capacitors C1a and C1b to
the output of the amplifier and switch S4c is closed.
The resulting differential voltages are held on capaci-
tors C2a and C2b. The amplifiers are used to charge
capacitors C1a and C1b to the same values originally
held on C2a and C2b. These values are then presented
to the first-stage quantizers and isolate the pipelines
from the fast-changing inputs. The wide input bandwidth
T/H amplifiers allow the MAX1183 to track-and-sam-
ple/hold analog inputs of high frequencies (> Nyquist).
Figure 2. MAX1183 T/H Amplifiers
INA+
INA-
INB+
INB-
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
S4a
S4b
S4a
S4b
S4c
S4c
Input Track-and-Hold (T/H) Circuits
C2a
C2b
C2a
C2b
INTERNAL
S2a
INTERNAL
INTERNAL
S2a
INTERNAL
BIAS
BIAS
BIAS
BIAS
S1
S1
S2b
S2b
______________________________________________________________________________________
Internal Reference and Parallel Outputs
C1a
C1b
C1a
C1b
COM
COM
COM
COM
S5a
S5b
S5a
S5b
S3a
S3b
S3a
S3b
OUT
OUT
OUT
OUT
HOLD
TRACK
HOLD
MAX1183
TRACK
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
The ADC inputs (INA+, INB+, INA- and INB-) can be
driven either differentially or single-ended. Match the
impedance of INA+ and INA-, as well as INB+ and INB-
and set the common-mode voltage to midsupply
(V
The full-scale range of the MAX1183 is determined by
the internally generated voltage difference between
REFP (V
V
adjustable through the REFIN pin, which is provided for
this purpose. REFOUT, REFP, COM (V
are internally buffered low-impedance outputs.
The MAX1183 provides three modes of reference
operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes, bypass REFIN with a >10nF capacitor to
GND. In internal reference mode, REFOUT, COM, REFP,
and REFN become low-impedance outputs.
In buffered external reference mode, adjust the reference
voltage levels externally by applying a stable and accu-
rate voltage at REFIN. In this mode, COM, REFP, and
REFN become outputs. REFOUT may be left open or
connected to REFIN through a >10kΩ resistor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut
down, these nodes become high impedance and may
be driven through separate external reference sources.
The MAX1183’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
REFIN
DD
/2) for optimum performance.
/4). The full-scale range for both on-chip ADCs is
DD
SNR
/2 + V
=
Analog Inputs and Reference
20
REFIN
×
log
⎛
⎜
⎝
/4) and REFN (V
2 π
× ×
Clock Input (CLK)
f
1
IN
Configurations
×
DD
t
AJ
/2), and REFN
⎞
⎟
⎠
DD
/2 -
11