MAX1183ECM+TD Maxim Integrated Products, MAX1183ECM+TD Datasheet - Page 17

IC ADC 10BIT 40MSPS DL 48-TQFP

MAX1183ECM+TD

Manufacturer Part Number
MAX1183ECM+TD
Description
IC ADC 10BIT 40MSPS DL 48-TQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX1183ECM+TD

Number Of Bits
10
Sampling Rate (per Second)
40M
Data Interface
Parallel
Number Of Converters
2
Power Dissipation (max)
180mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V
V
harmonics.
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
5
are the amplitudes of the 2nd- through 5th-order
THD
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Signal-to-Noise Plus Distortion (SINAD)
Spurious-Free Dynamic Range (SFDR)
1
=
is the fundamental amplitude, and V
20
×
Total Harmonic Distortion (THD)
log
GND
INA+
INA-
CLK
10
V
INB+
INB-
______________________________________________________________________________________
DD
Internal Reference and Parallel Outputs
V
2
2
+
V
3
2
REFOUT
V
+
1
T/H
T/H
V
4
2
+
REFN COM REFP
V
CONTROL
5
2
2
REFERENCE
through
PIPELINE
PIPELINE
ADC
ADC
REFIN
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are backed off by 6.5dB from full scale.
Table 2. Pin-Compatible Versions
MAX1190
MAX1180
MAX1181
MAX1182
MAX1183
MAX1186
MAX1184
MAX1185
MAX1198
MAX1197
MAX1196
MAX1195
PART
DEC
DEC
10
RESOLUTION
10
Intermodulation Distortion (IMD)
(BITS)
10
10
10
10
10
10
10
10
8
8
8
8
MAX1183
DRIVERS
OUTPUT
DRIVERS
OUTPUT
Functional Diagram
GRADE
SPEED
10
(Msps)
10
120
105
100
80
65
40
40
20
20
60
40
40
OE
OGND
OV
T/B
D9A–D0A
PD
SLEEP
D9B–D0B
DD
Full-Duplex
Full-Duplex
Full-Duplex
Full-Duplex
Full-Duplex
Half-Duplex
Full-Duplex
Half-Duplex
Full-Duplex
Full-Duplex
Half-Duplex
Full-Duplex
OUTPUT
BUS
17

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