MAX1301BEUP+ Maxim Integrated Products, MAX1301BEUP+ Datasheet - Page 15

• Manufacturer Part Number: MAX1301BEUP+
• Description: IC ADC 16BIT SER 4CH LP 20TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1301BEUP+

• Number Of Bits: 16
• Sampling Rate (per Second): 115k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 105.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2. External Clock-Mode Conversion (Mode 0)
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When
configuring differential channels, the differential pair fol-
lows the analog configuration byte for the positive
channel. For example, to configure CH2 and CH3 for a
±3 x V
configuration byte for a differential conversion with the
±3 x V
for the CH2 and CH3 differential pair, issue the com-
mand 1010 0000.
8- and 4-Channel, ±3 x V
SSTRB
TRACK AND HOLD*
DOUT
SCLK
DIN
CS
ANALOG INPUT
REF
REF
IMPEDANCE
HIGH
range (1010 1100). To initiate a conversion
differential conversion, set the CH2 analog
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
S
HOLD
C2
______________________________________________________________________________________
C1
C0
0
BYTE 1
0
0
0
TRACK
t
ACQ
BYTE 2
f
SAMPLE
≈ f
SAMPLING INSTANT
SCLK
/ 32
The MAX1300/MAX1301 input-tracking circuitry has a
2MHz small-signal bandwidth. The 2MHz input band-
width makes it possible to digitize high-speed transient
events. Harmonic distortion increases when digitizing
signal frequencies above 15kHz as shown in the THD
and -SFDR vs. Input Frequency plot in the Typical
Operating Characteristics .
Figure 7 illustrates the software-selectable single-ended
analog input voltage range that produces a valid digital
output. Each analog input channel can be independently
programmed to one of seven single-ended input ranges
by setting the R[2:0] control bits with DIF/SGL = 0.
B15
REF
B14
Analog Input Range and Fault Tolerance
B13
B12
BYTE 3
Serial 16-Bit ADCs
Multirange Inputs,
B11
B10
B9
HOLD
B8
B7
Analog Input Bandwidth
B6
B5
B4
BYTE 4
B3
B2
B1
B0
IMPEDANCE
HIGH
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