CS5102A-JLZ Cirrus Logic Inc, CS5102A-JLZ Datasheet - Page 5

• Manufacturer Part Number: CS5102A-JLZ
• Description: IC ADC 16BIT 100/20KHZ 28-PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5102A-JLZ

• Number Of Bits: 16
• Sampling Rate (per Second): 20k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 65mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1080-5

ANALOG CHARACTERISTICS, CS5101A
Notes:
DS45F6
Specified Temperature Range
Analog Input
Aperture Time
Aperture Jitter
Input Capacitance
Conversion and Throughput
Conversion Time
Acquisition Time
Throughput
Power Supplies
Power Supply Current
(SLEEP High)
Power Consumption
Power Supply Rejection
10. Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low).
11. With 300 mV p-p, 1-kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB
5. Applies only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.
6. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback
7. The CS5101A requires 6 clock cycles of coarse charge, followed by a minimum of 1.125 µs of fine charge. FRN
8. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting
9. All outputs unloaded. All inputs at VD+ or DGND.
(FRN) mode) with 8.0 MHz CLKIN. In PDT, RBT, and SSC modes, asynchronous delay between the falling edge
of
master clock cycles + 10 ns. In PDT, RBT, and SSC modes, CLKIN can be increased as long as the
rate is 100 kHz max.
mode allows 9 cycles for fine charge which provides for the minimum 1.125 µs with an 8MHz clock, however; in
PDT, RBT, or SSC modes and at clock frequencies of 8 MHz or less, fine charge may be less than 9 clock cycles.
This reflects the typical specification (6 clock cycles + 1.125 µs).
acquisition and conversion times, as described above.
in the unipolar mode to 90 dB. Figure 25 shows a plot of typical power supply rejection versus frequency.
HOLD
Parameter*
and the start of conversion may add to the apparent conversion time. This delay will not exceed 1.5
Negative Supplies
Positive Supplies
Negative Analog
Negative Digital
Positive Analog
Unipolar Mode
Positive Digital
(SLEEP High)
(SLEEP Low)
Bipolar Mode
(Note 9, Note 10)
(Note 11)
(Note 6)
(Note 7)
(Note 8)
(Note 9)
(Note 5)
Symbol
PSR
PSR
P
I
P
I
I
I
f
A
D
t
t
D
A
tp
-
-
-
-
-
c
a
do
ds
+
+
-
-
(Continued)
Min
100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS5101A-J
0 to +70
Typ
100
320
200
320
-21
-11
25
21
84
84
11
1
-
-
-
Max
8.12
1.88
425
265
430
-28
-15
28
15
-
-
-
-
-
-
CS5101A CS5102A
Min
100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS5101A-B
-40 to +85
Typ
100
320
200
320
-21
-11
25
21
84
84
11
1
-
-
-
Max
8.12
1.88
425
265
430
-28
-15
28
15
HOLD
-
-
-
-
-
-
kSps
sample
Unit
mW
mW
mA
mA
mA
mA
pF
pF
dB
dB
ºC
ns
ps
µs
µs
5