CS5102A-JLZ Cirrus Logic Inc, CS5102A-JLZ Datasheet - Page 8

IC ADC 16BIT 100/20KHZ 28-PLCC

CS5102A-JLZ

Manufacturer Part Number
CS5102A-JLZ
Description
IC ADC 16BIT 100/20KHZ 28-PLCC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5102A-JLZ

Number Of Bits
16
Sampling Rate (per Second)
20k
Data Interface
Serial
Number Of Converters
1
Power Dissipation (max)
65mW
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1080-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5102A-JLZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS5102A-JLZ
Manufacturer:
CRYSTAL
Quantity:
20 000
ANALOG CHARACTERISTICS, CS5102A
Notes:
8
Specified Temperature Range
Analog Input
Aperture Time
Aperture Jitter
Input Capacitance
Conversion and Throughput
Conversion Time
Acquisition Time
Throughput
Power Supplies
Power Supply Current
(SLEEP High)
Power Consumption
Power Supply Rejection
17. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback
18. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge. FRN
19. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting
20. All outputs unloaded. All inputs at VD+ or DGND. See table below for power dissipation versus clock frequency.
21. With 300 mV p-p, 1-kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB
(FRN) mode. In PDT, RBT, and SSC modes, asynchronous delay between the falling edge of
of conversion may add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns.
mode allows 9 cycles for fine charge which provides for the minimum 5.625 µs with a 1.6 MHz clock, however; in
PDT, RBT, or SSC modes and at clock frequencies of less than 1.6 MHz, fine charge may be less than 9 clock
cycles.
acquisition and conversion times, as described above.
in the unipolar mode to 90 dB. Figure 25 shows a plot of typical power supply rejection versus frequency.
Parameter*
Negative Supplies
Positive Supplies
Negative Analog
Negative Digital
Positive Analog
Unipolar Mode
Positive Digital
(SLEEP High)
(SLEEP Low)
Bipolar Mode
Typical Power (mW)
(Note 10, Note 20)
34
37
39
41
44
(Note 17)
(Note 18)
(Note 19)
(Note 20)
(Note 21)
(Note 5)
Symbol
PSR
PSR
P
I
P
I
I
I
f
A
D
t
t
D
A
tp
-
-
-
-
-
c
a
do
ds
+
+
-
-
(Continued)
CLKIN (MHz)
Min
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS5102A-J
0.8
1.0
1.2
1.4
1.6
0 to +70
Typ
100
320
200
-2.4
-1.5
2.4
2.5
30
44
84
84
1
-
-
-
40.625
9.375
Max
-3.5
-2.5
425
265
3.5
3.5
65
-
-
-
-
-
-
CS5101A CS5102A
Min
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS5102-B
-40 to +85
Typ
100
320
200
-2.4
-1.5
2.4
2.5
30
44
84
84
1
-
-
-
HOLD
40.625
9.375
Max
-3.5
-2.5
425
265
3.5
3.5
65
-
-
-
-
-
-
and the start
DS45F6
kSps
Unit
mW
mW
mA
mA
mA
mA
dB
dB
ºC
ns
pF
pF
µs
µs
ps

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