CAT5411WI-50-T1 ON Semiconductor, CAT5411WI-50-T1 Datasheet - Page 3

• Manufacturer Part Number: CAT5411WI-50-T1
• Description: IC POT DPP 50K 64TAP SPI 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5411WI-50-T1

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
SI: Serial Input
opcodes, byte addresses and data to be written to the
CAT5411. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
data out of the CAT5411. During a read cycle, data is shifted
out on the falling edge of the serial clock.
SCK: Serial Clock
the communication between the microcontroller and the
CAT5411. Opcodes, byte addresses or data present on the SI
pin are latched on the rising edge of the SCK. Data on the SO
pin is updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
multiple devices. A total of four devices can be addressed on
a single bus. A match in the slave address must be made with
the address input in order to initiate communication with the
CAT5411.
R
terminal connections on a mechanical potentiometer.
R
a mechanical potentiometer.
H
W
SI is the serial data input pin. This pin is used to input all
SO is the serial data output pin. This pin is used to transfer
SCK is the serial clock pin. This pin is used to synchronize
These inputs set the device address when addressing
The four sets of R
The four R
, R
: Wiper
L
: Resistor End Points
W
pins are equivalent to the wiper terminal of
H
and R
L
SCK
pins are equivalent to the
WP
SO
CS
A0
A1
SI
INTERFACE
CONTROL
SPI BUS
LOGIC
Figure 1. Functional Diagram
http://onsemi.com
NONVOLATILE
REGISTERS
REGISTERS
CONTROL
3
WIPER
DATA
CS: Chip Select
takes the SO output pin to high impedance and forces the
devices into a Standby mode (unless an internal write
operation is underway). The CAT5411 draws ZERO current
in the Standby mode. A high to low transition on CS is
required prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what initiates
an internal write cycle.
WP: Write Protect
allow normal read/write operations when held high. When
WP is tied low, all non−volatile write operations to the Data
registers are inhibited (change of wiper control register is
allowed). WP going low while CS is still low will interrupt
a write to the registers. If the internal write cycle has already
been initiated, WP going low will have no effect on any write
operation.
HOLD: Hold
CAT5411 while in the middle of a serial sequence without
having to re−transmit entire sequence at a later time. To
pause, HOLD must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part
is paused, and transitions on the SI pins will be ignored. To
resume communication, HOLD is brought high, while SCK
is low. (HOLD should be held high any time this function is
not being used.) HOLD may be tied high directly to V
tied to V
CAT5251 and CS high disables the CAT5411. CS high
WP is the Write Protect pin. The Write Protect pin will
The HOLD pin is used to pause transmission to the
CC
R
R
H0
L0
through a resistor.
R
R
H1
L1
R
R
W0
W1
CC
or