CAT5411WI-50-T1 ON Semiconductor, CAT5411WI-50-T1 Datasheet - Page 4

• Manufacturer Part Number: CAT5411WI-50-T1
• Description: IC POT DPP 50K 64TAP SPI 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5411WI-50-T1

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Operation
serial interface logic, two 6−bit wiper control registers and
eight 6−bit, non−volatile memory data registers. Each resistor
array contains 63 separate resistive elements connected in
series. The physical ends of each array are equivalent to the
fixed terminals of a mechanical potentiometer (R
R
positions between and at the ends of the series resistors are
connected to the output wiper terminals (R
transistor switch. Only one tap point for each potentiometer
is connected to its wiper terminal at a time and is determined
by the value of the wiper control register. Data can be read or
written to the wiper control registers or the non−volatile
memory data registers via the SPI bus. Additional instructions
allow data to be transferred between the wiper control
1. This parameter is tested initially and after a design or process change that affects the parameter.
Table 2. RELIABILITY CHARACTERISTICS
Table 1. PIN CONNECTIONS
H
The CAT5411 is two resistor arrays integrated with SPI
N
V
TDR (Note 1)
Pin SOIC
I
and R
LTH
END
ZAP
Symbol
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
1
2
3
4
5
6
7
8
9
(Note 1)
(Note 1)
(Note 1)
L
are symmetrical and may be interchanged. The tap
Pin TSSOP
Endurance
Data Retention
ESD Susceptibility
Latch−Up
19
20
21
22
23
24
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Parameter
Name
HOLD
GND
SCK
R
R
V
R
R
R
WP
R
CS
NC
NC
NC
NC
SO
NC
NC
NC
NC
A
A
SI
CC
W0
W1
H0
H1
L0
L1
1
0
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
W
) by a CMOS
Reference Test Method
(Over recommended operating conditions unless otherwise stated.)
Supply Voltage
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Hold
Serial Data Output
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
H
and R
http://onsemi.com
L
).
4
registers and each respective potentiometer’s non−volatile
data registers. Also, the device can be instructed to operate in
an “increment/decrement” mode.
Serial Bus Protocol
protocol. The synchronous Serial Peripheral Interface (SPI)
helps the CAT5411 to interface directly with many of
today’s popular microcontrollers. The CAT5041 contains an
8−bit instruction register. The instruction set and the
operation codes are detailed in the instruction set Table 12.
byte will be received. The part is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The first
byte contains one of the six op−codes that define the
operation to be performed.
The CAT5041 supports the SPI bus data transmission
After the device is selected with CS going low the first
1,000,000
Function
2000
Min
100
100
Typ
Max
Cycles/Byte
Years
Units
Volts
mA