CAT5411WI-50-T1 ON Semiconductor, CAT5411WI-50-T1 Datasheet - Page 9

• Manufacturer Part Number: CAT5411WI-50-T1
• Description: IC POT DPP 50K 64TAP SPI 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5411WI-50-T1

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Wiper Control and Data Registers
Wiper Control Register (WCR)
Registers, one for each potentiometer. The Wiper Control
Register output is decoded to select one of 64 switches along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written by the host via Write Wiper
Control Register instruction; it may be written by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction, it can be
modified one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register zero
(DR0) upon power−up.
its contents when the CAT5411 is powered−down. Although
the register is automatically loaded with the value in DR0
upon power−up, this may be different from the value present
at power−down.
Data Registers (DR)
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Table 12. INSTRUCTION SET
Read Wiper Control Register
Write Wiper Control Register
Read Data Register
Write Data Register
XFR Data Register to Wiper
Control Register
XFR Wiper Control Register
to Data Register
Global XFR Data Registers
to Wiper Control Registers
Global XFR Wiper Control
Registers to Data Register
Increment/Decrement
Wiper Control Register
Read Status
The CAT5411 contains two 6−bit Wiper Control
The Wiper Control Register is a volatile register that loses
Each potentiometer has four 6−bit non−volatile Data
Instruction
I3
1
1
1
1
1
1
0
1
0
0
(Note: 1/0 = data is one or zero)
I2
0
0
0
1
1
1
0
0
0
1
I1
0
1
1
0
0
1
0
0
1
0
I0
1
0
1
0
1
0
1
0
0
1
Instruction Set
1/0
1/0
1/0
1/0
1/0
1/0
R1
0
0
0
0
http://onsemi.com
1/0
1/0
1/0
1/0
1/0
1/0
R0
0
0
0
0
9
0
0
0
0
0
0
0
0
0
0
0
Registers and the associated Wiper Control Register. Any
data changes in one of the Data Registers is a non−volatile
operation and will take a maximum of 5 ms.
Write in Process
nonvolatile memory when the CS input goes HIGH after a
write sequence is received. The status of the internal write
cycle can be monitored by issuing a Read Status command
to read the Write in Process (WIP) bit.
INSTRUCTIONS
instructions are:
•
•
•
•
•
The contents of the Data Registers are saved to
Four of the ten instructions are three bytes in length. These
Read Wiper Control Register – read the current wiper
position of the selected potentiometer in the WCR
Write Wiper Control Register – change current wiper
position in the WCR of the selected potentiometer
Read Data Register – read the contents of the selected
Data Register
Write Data Register – write a new value to the
selected Data Register
Read Status – Read the status of the WIP bit which
when set to “1” signifies a write cycle is in progress.
WCR
1/0
1/0
1/0
1/0
1/0
1/0
1/0
0
0
1
0
/ P0
Read the contents of the Wiper Control
Register pointed to by P0
Write new value to the Wiper Control Register
pointed to by P0
Read the contents of the Data Register pointed
to by P0 and R1−R0
Write new value to the Data Register pointed
to by P0 and R1−R0
Transfer the contents of the Data Register
pointed to by P0 and R1−R0 to its associated
Wiper Control Register
Transfer the contents of the Wiper Control
Register pointed to by P0 to the Data Register
pointed to by R1−R0
Transfer the contents of the Data Registers
pointed to by R1−R0 of all four pots to their
respective Wiper Control Registers
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1−R0 of all four pots
Enable Increment/decrement of the Control
Latch pointed to by P0
Read WIP bit to check internal write cycle
status
Operations