CAT5411WI-50-T1 ON Semiconductor, CAT5411WI-50-T1 Datasheet - Page 8

• Manufacturer Part Number: CAT5411WI-50-T1
• Description: IC POT DPP 50K 64TAP SPI 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT5411WI-50-T1

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Instruction and Register Description
Device Type / Address Byte
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a device
type identifier. These bits for the CAT5411 are fixed at
0101[B] (refer to Figure 4).
− A0, are the internal slave address and must match the
physical device address which is defined by the state of the A1
− A0 input pins for the CAT5411 to successfully continue the
command sequence. Only the device which slave address
matches the incoming device address sent by the master
executes the instruction. The A1 − A0 inputs can be actively
driven by CMOS input signals or tied to V
remaining two bits in the device address byte must be set to 0.
The first byte sent to the CAT5411 from the master/
The two least significant bits in the slave address byte, A1
HOLD
V
SCK
W
SCK
CS
SO
/R
CS
SO
SI
W
High Impedance
(MSB)
(MSB)
ID3
I3
0
Figure 4. Identification Byte Format 0101 Device Type Identifier (MSB)
MSB
Device Type Identifier
Instruction Opcode
ID2
I2
Figure 6. Potentiometer Timing (for All Load Instructions)
1
t
HD
t
CD
ID1
I1
CC
Figure 5. Instruction Byte Format
0
t
HZ
or V
Figure 3. HOLD Timing
SS
http://onsemi.com
. The
ID0
I0
1
8
HIGH IMPEDANCE
Data Register Selection
Instruction Byte
and register pointer information. The four most significant
bits used provide the instruction opcode I [3:0]. The R1 and
R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits point
to one of two Wiper Control Registers. The format is shown
in Figure 5.
Table 11. DATA REGISTER SELECTION
R1
0
. . .
The next byte sent to the CAT5411 contains the instruction
. . .
t
HD
Data Register Selected
R0
0
t
Slave Address
WRL
DR0
DR1
DR2
DR3
LSB
t
CD
t
LZ
A1
0
WCR/Pot Selection
(LSB)
(LSB)
P0
A0
R1
0
0
1
1
R0
0
1
0
1