CS4384-CQZ Cirrus Logic Inc, CS4384-CQZ Datasheet - Page 24

IC DAC 8CH 103DB 192KHZ 48LQFP

CS4384-CQZ

Manufacturer Part Number
CS4384-CQZ
Description
IC DAC 8CH 103DB 192KHZ 48LQFP
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS4384-CQZ

Data Interface
Serial
Number Of Bits
24
Number Of Converters
8
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
520mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
24bit
Sampling Rate
192kSPS
Input Channel Type
Serial
Supply Voltage Range - Analog
4.75V To 5.25V
Supply Current
83mA
Digital Ic Case Style
QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1525 - BOARD EVAL FOR CS4384 DAC
Settling Time
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1062

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4384-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS4384-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
SDIN1
LRCK
SCLK
24
4.3.3
4.3.4
4.3.5
LRCK
SCLK
SDIN1
LRCK
SCLK
SDIN1
LSB
MSB
MSB
OLM #3
OLM #3 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to
SCLK at 256 Fs. Eight channels of MSB first 20-bit PCM data are input on SDIN1.
OLM #4
OLM #4 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to
SCLK at 256 Fs. Eight channels of MSB first 24-bit PCM data are input on SDIN1.
TDM
The TDM serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave
to SCLK at 256 Fs. Data is received most significant bit first on the first SCLK after an LRCK transition
and is valid on the rising edge of SCLK. LRCK identifies the start of a new frame and is equal to the sample
rate, Fs. LRCK is sampled as valid on the rising SCLK edge preceding the most significant bit of the first
data sample and must be held valid for one SCLK period. Each time slot is 32 bits wide, with the valid data
sample left justified within the time slot with the remaining bits being zero padded.
DAC_A1
DAC_A1
20 clks
24 clks
MSB
MSB
DAC_A1
32 clks
LSB
LSB
Data
MSB
MSB
LSB
LSB
DAC_A2
DAC_A2
Left Channel
20 clks
Left Channel
24 clks
128 clks
128 clks
MSB
LSB
LSB
DAC_B1
32 clks
zero
MSB
MSB
LSB
DAC_A3
DAC_A3
20 clks
24 clks
Figure 17. Format 10 - One Line Mode 3
Figure 18. Format 11 - One Line Mode 4
MSB
Figure 19. Format 12 - TDM Mode
LSB
LSB
DAC_A2
32 clks
MSB
MSB
DAC_A4
DAC_A4
20 clks
24 clks
LSB
MSB
LSB
LSB
DAC_B2
32 clks
256 clks
MSB
MSB
LSB
DAC_B1
DAC_B1
20 clks
24 clks
MSB
DAC_A3
32 clks
LSB
LSB
MSB
MSB
LSB
DAC_B2
DAC_B2
Right Channel
Right Channel
20 clks
24 clks
128 clks
128 clks
MSB
LSB
LSB
DAC_B3
32 clks
MSB
MSB
DAC_B3
DAC_B3
LSB
20 clks
24 clks
MSB
LSB
LSB
DAC_A4
32 clks
MSB
MSB
DAC_B4
DAC_B4
20 clks
24 clks
LSB
MSB
LSB
LSB
CS4384
DS620F1
DAC_B4
32 clks
MSB
MSB
LSB

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