CS4384-CQZ Cirrus Logic Inc, CS4384-CQZ Datasheet - Page 3

• Manufacturer Part Number: CS4384-CQZ
• Description: IC DAC 8CH 103DB 192KHZ 48LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4384-CQZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 83mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1525 - BOARD EVAL FOR CS4384 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1062

DS620F1
7. FILTER RESPONSE PLOTS ............................................................................................................... 45
8. REFERENCES...................................................................................................................................... 49
9. PARAMETER DEFINITIONS................................................................................................................ 49
10. PACKAGE DIMENSIONS .................................................................................................................. 50
11. ORDERING INFORMATION .............................................................................................................. 51
12. REVISION HISTORY ......................................................................................................................... 51
6.3 PCM Control (Address 03h) .......................................................................................................... 36
6.4 DSD Control (Address 04h) ........................................................................................................... 37
6.5 Filter Control (Address 05h) .......................................................................................................... 39
6.6 Invert Control (Address 06h) ......................................................................................................... 39
6.7 Group Control (Address 07h) ........................................................................................................ 39
6.8 Ramp and Mute (Address 08h) ..................................................................................................... 40
6.9 Mute Control (Address 09h) .......................................................................................................... 42
6.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h) ............................................................................. 42
6.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h)........................................... 44
6.12 PCM Clock Mode (Address 16h) ................................................................................................. 44
6.2.3 PCM/DSD Selection (DSD/PCM)......................................................................................... 36
6.2.4 DAC Pair Disable (DACx_DIS) ............................................................................................ 36
6.2.5 Power Down (PDN).............................................................................................................. 36
6.3.1 Digital Interface Format (DIF)............................................................................................... 36
6.3.2 Functional Mode (FM) .......................................................................................................... 37
6.4.1 DSD Mode Digital Interface Format (DSD_DIF) .................................................................. 37
6.4.2 Direct DSD Conversion (DIR_DSD)..................................................................................... 38
6.4.3 Static DSD Detect (STATIC_DSD) ...................................................................................... 38
6.4.4 Invalid DSD Detect (INVALID_DSD).................................................................................... 38
6.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE).................................................... 38
6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) ........................................................ 38
6.5.1 Interpolation Filter Select (FILT_SEL).................................................................................. 39
6.6.1 Invert Signal Polarity (INV_xx) ............................................................................................. 39
6.7.1 Mutec Pin Control (MUTEC) ................................................................................................ 39
6.7.2 Channel A Volume = Channel B Volume (Px_A=B)............................................................. 39
6.7.3 Single Volume Control (SNGLVOL) ..................................................................................... 40
6.8.1 Soft Ramp and Zero Cross Control (SZC) ........................................................................... 40
6.8.2 Soft Volume Ramp-Up After Error (RMP_UP) ..................................................................... 41
6.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) ................................................... 41
6.8.4 PCM Auto-Mute (PAMUTE) ................................................................................................. 41
6.8.5 DSD Auto-Mute (DAMUTE) ................................................................................................. 41
6.8.6 MUTE Polarity and DETECT (MUTEP1:0)........................................................................... 41
6.9.1 Mute (MUTE_xx) .................................................................................................................. 42
6.10.1 De-Emphasis Control (PX_DEM1:0).................................................................................. 42
6.10.2 ATAPI Channel Mixing and Muting (ATAPI) ...................................................................... 43
6.11.1 Digital Volume Control (xx_VOL7:0) .................................................................................. 44
6.12.1 Master Clock Divide by 2 Enable (MCLKDIV).................................................................... 44
CS4384
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