CS4384-CQZ Cirrus Logic Inc, CS4384-CQZ Datasheet - Page 31

• Manufacturer Part Number: CS4384-CQZ
• Description: IC DAC 8CH 103DB 192KHZ 48LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4384-CQZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 83mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1525 - BOARD EVAL FOR CS4384 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1062

DS620F1
4.14.3 SPI Mode
4.14.2.2 I²C Read
To read from the device, follow the procedure below while adhering to the control port Switching Specifica-
tions.
4.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifica-
tions in
1.
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con-
5. If the INCR bit is set to 0 and further
1.
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see
is used to control SPI writes to the control port. When the device detects a high to low transition on the
AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
pointed to by the MAP. The MAP register will contain the address of the last register written to the
MAP, or the default address (see
device.
tinue providing a clock and issue an ACK after each byte until all the desired registers are read, then
initiate a STOP condition to the bus.
a repeated START condition and follow the procedure detailed from steps 1 and 2 from the
instructions followed by step 1 of the
sired, initiate a STOP condition to the bus.
are written, then bring CS high.
Initiate a START condition to the
Bring CS low.
Figure 27
Section
S C L
S D A
N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P .
2.
for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
S ta rt
0 01 1 00
Section
Figure 26. Control Port Timing, I²C Mode
A D D R
AD 0
4.14.1) is set to 1, repeat the previous step until all the desired registers
Section
I²C
R /W
I²C
I²C
bus followed by the address byte. The upper 6 bits must be
reads from other registers are desired, it is necessary to initiate
Read section. If no further reads from other registers are de-
A C K
4.14.1) if an
D AT A
1-8
N o te 1
I²C
A C K
read is the first operation performed on the
D A TA
1-8
A C K
S top
CS4384
I²C
Write
31