AD9763ASTZ Analog Devices Inc, AD9763ASTZ Datasheet - Page 14

• Manufacturer Part Number: AD9763ASTZ
• Description: IC DAC 10BIT DUAL 125MSPS 48LQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9763ASTZ

• Data Interface: Parallel
• Settling Time: 35ns
• Number Of Bits: 10
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 450mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 10bit
• Sampling Rate: 125MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 3V To 5.5V
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9763-EBZ - BOARD EVAL FOR AD9763
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9763
I
nominally set by a reference voltage (V
resistor R
where I
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, I
should be directly connected to matching resistive loads (R
that are tied to the analog common (ACOM). Note that R
can represent the equivalent load resistance seen by I
I
The single-ended voltage output appearing at the I
nodes is simply
The full-scale value of V
specified output compliance range to maintain specified
distortion and linearity performance.
Substituting the values of I
expressed as
Equation 7 and Equation 8 highlight some of the advantages of
operating the AD9763 differentially. First, the differential
operation helps cancel common-mode error sources associated
with I
Second, the differential code-dependent current and subsequent
voltage, V
output (V
to the load.
The gain drift temperature performance for a single-ended
(V
can be enhanced by selecting temperature tracking resistors for
R
Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, I
I
I
ended voltage outputs, V
(R
differential voltage (V
also be converted to a single-ended voltage via a transformer or
differential amplifier configuration. The ac performance of the
AD9763 is optimum and specified using a differential transformer
coupled output where the voltage swing at I
OUTFS
OUTB
OUTB
OUTA
LOAD
LOAD
OUTA
I
, as is the case in a doubly terminated 50 Ω or 75 Ω cable.
B
V
V
V
V
(32 × R
, can be configured for single-ended or differential operation.
B
and I
OUTFS
is a function of the reference current I
OUTA
and R
OUTA
OUTB
DIFF
DIFF
) as described in Equation 5 through Equation 8. The
and V
REF
SET
OUTA
DIFF
= (I
= {(2 × DAC CODE − 1023)/1024} ×
= V
and I
= 32 × I
OUTB
= I
= I
. It can be expressed as
SET
LOAD
, is twice the value of the single-ended voltage
OUTB
OUTB
OUTA
OUTA
REFIO
or V
due to their ratiometric relationship, as shown in
can be converted into complementary single-
OUTB
/R
) or differential output (V
B
× R
/R
× R
− I
SET
REF
OUTB
B
such as noise, distortion, and dc offsets.
SET
) × V
OUTB
LOAD
LOAD
DIFF
) , thus providing twice the signal power
B
OUTA
) × R
OUTA
) existing between V
REFIO
OUTA
and V
and V
LOAD
, I
OUTB
OUTB
OUTB
, and I
B
REFIO
B
should not exceed the
B
via a load resistor
REF
DIFF
) and external
OUTA
REF
, V
OUTA
) of the AD9763
. This is
OUTA
and I
DIFF
and V
OUTA
can be
OUTA
and I
OUTA
OUTB
and I
OUTB
and
B
or
LOAD
is
OUTB
LOAD
B
OUTB
Rev. D | Page 14 of 32
can
(4)
(3)
(5)
(6)
(7)
(8)
)
limited to ±0.5 V. If a single-ended unipolar output is desired,
I
The distortion and noise performance of the AD9763 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both I
significantly reduced by the common-mode rejection of a trans-
former or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi-
cant as the frequency content of the reconstructed waveform
increases. This is due to the first order cancellation of various
dynamic common-mode distortion mechanisms, digital feed-
through, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the recon-
structed signal power to the load, assuming no source
termination. Because the output currents of I
complementary, they become additive when processed differen-
tially. A properly selected transformer allows the AD9763 to
provide the required power and voltage levels to different loads.
The output impedance of I
equivalent parallel combination of the PMOS switches associ-
ated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(V
result, maintaining I
I-V op amp configuration results in the optimum dc linearity.
The INL/DNL specifications for the AD9763 are measured with
I
I
ance range that must be adhered to in order to achieve optimum
performance. The negative output compliance range of −1.0 V
is set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit can result in a breakdown of the
output stage and affect the reliability of the AD9763.
The positive output compliance range is slightly dependent on
the full-scale output current, I
its nominal 1.25 V for an I
I
ended or differential output is achieved when the maximum
full-scale signal at I
Applications requiring the AD9763 output (V
to extend its output compliance range should size R
accordingly. Operation beyond this compliance range adversely
affects the linearity performance of the AD9763 and
subsequently degrades its distortion performance.
OUTA
OUTA
OUTA
OUTFS
OUTA
should be selected.
maintained at a virtual ground via an op amp.
and I
= 2 mA. The optimum distortion performance for a single-
and V
OUTB
OUTB
also have a negative and positive voltage compli-
) due to the nature of a PMOS device. As a
B
OUTA
OUTA
and I
and/or I
OUTA
OUTFS
OUTB
OUTFS
and I
= 20 mA to 1.00 V for an
OUTB
does not exceed 0.5 V.
. It degrades slightly from
OUTB
B
at a virtual ground via an
OUTA
B
is determined by the
and I
OUTA
OUTA
OUTB
and I
and/or V
LOAD
B
can be
OUTB
B
are
OUTB
)
B