AD9763ASTZ Analog Devices Inc, AD9763ASTZ Datasheet - Page 19

• Manufacturer Part Number: AD9763ASTZ
• Description: IC DAC 10BIT DUAL 125MSPS 48LQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9763ASTZ

• Data Interface: Parallel
• Settling Time: 35ns
• Number Of Bits: 10
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 450mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 10bit
• Sampling Rate: 125MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 3V To 5.5V
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9763-EBZ - BOARD EVAL FOR AD9763
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The differential circuit shown in Figure 37 provides the necessary
level shifting required in a single-supply system. In this case,
AVDD, the positive analog supply for both the AD9763 and the
op amp, is also used to level shift the differential output of the
AD9763 to midsupply (AVDD/2). The AD8055 is a suitable op
amp for this application.
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 38 shows the AD9763 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly termi-
nated 50 Ω cable because the nominal full-scale current (I
of 20 mA flows through the equivalent R
case, R
I
to ACOM directly or via a matching R
I
range is adhered to. One additional consideration in this mode
is the integral nonlinearity (INL) as described in the Analog
Outputs section. For optimum INL performance, the single-
ended, buffered voltage output configuration is suggested.
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
Figure 39 shows a buffered, single-ended output configuration
where the Op Amp U1 performs an I-V conversion on the
AD9763 output current. U1 maintains I
virtual ground, thus minimizing the nonlinear output impedance
effect on the DAC INL performance, as described in the Analog
Outputs section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates can be
limited by slewing capabilities of U1. U1 provides a negative
unipolar output voltage and its full-scale output voltage is
simply the product of R
within voltage output swing capabilities of U1 by scaling I
and/or R
result with a reduced I
required to sink is subsequently reduced.
OUTA
OUTFS
AD9763
or I
AD9763
and R
LOAD
FB
Figure 37. Single-Supply DC Differential Coupled Circuit
OUTB
I
I
OUTA
OUTB
. An improvement in ac distortion performance can
represents the equivalent load resistance seen by
Figure 38. 0 V to 0.5 V Unbuffered Voltage Output
LOAD
I
I
OUTA
OUTB
. The unused output (I
can be selected as long as the positive compliance
25Ω
I
OUTFS
C
OUTFS
OPT
FB
25Ω
= 20mA
and I
because the signal current U1 is
25Ω
OUTFS
225Ω
225Ω
50Ω
OUTA
. Set the full-scale output
LOAD
or I
OUTA
500Ω
LOAD
OUTB
. Different values of
V
AD8055
OUTA
(or I
of 25 Ω. In this
500Ω
) can be connected
1kΩ
50Ω
= 0V TO 0.5V
OUTB
) at a
AVDD
OUTFS
OUTFS
Rev. D | Page 19 of 32
)
POWER AND GROUNDING CONSIDERATIONS,
POWER SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit board
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing, as well as
power supply bypassing and grounding to ensure optimum per-
formance. Figure 46 to Figure 53 illustrate the recommended
printed circuit board ground, power, and signal plane layouts
that are implemented on the AD9763 evaluation board.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the full-scale current (I
supplies is common in applications where the power distribution
is generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum from tens of kHz
to several MHz. The PSRR vs. frequency of the AD9763 AVDD
supply over this frequency range is shown in Figure 40.
AD9763
I
I
OUTA
OUTB
90
85
80
75
70
0.2
Figure 39. Unipolar Buffered Voltage Output
0.3
Figure 40. Power Supply Rejection Ratio
I
OUTFS
0.4
OUTFS
= 10mA
0.5
FREQUENCY (MHz)
200Ω
) of the DAC. AC noise on the dc
0.6
0.7
C
200Ω
R
U1
OPT
FB
0.8
0.9
V
OUT
= I
1.0
AD9763
OUTFS
1.1
× R
FB