CY8C5387AXI-108 Cypress Semiconductor Corp, CY8C5387AXI-108 Datasheet - Page 13

• Manufacturer Part Number: CY8C5387AXI-108
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5387AXI-108

• Lead Free Status / Rohs Status: Compliant

Table 4-4. Priority Levels
4.3.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.3.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location).
4.3.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is repet-
itively read from system memory and written to a peripheral. This
is done with a single TD that chains to itself.
4.3.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.3.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
4.3.4.5 Indexed DMA
In an indexed DMA case, an external master requires access to
locations on the system bus as if those locations were shared
memory. As an example, a peripheral may be configured as an
SPI or I
master. That address becomes an index or offset into the internal
system bus memory space. This is accomplished with an initial
“address fetch” TD that reads the target address location from
the peripheral and writes that value into a subsequent TD in the
Document Number: 001-55035 Rev. *F
Priority Level
2
C slave where an address is received by the external
0
1
2
3
4
5
6
7
% Bus Bandwidth
100.0
100.0
50.0
25.0
12.5
6.2
3.1
1.5
PRELIMINARY
chain. This modifies the TD chain on the fly. When the “address
fetch” TD completes it moves on to the next TD, which has the
new address information embedded in it. This TD then carries
out the data transfer with the address location required by the
external master.
4.3.4.6 Scatter Gather DMA
In the case of scatter gather DMA, there are multiple noncon-
tiguous sources or destinations that are required to effectively
carry out an overall DMA transaction. For example, a packet may
need to be transmitted off of the device and the packet elements,
including the header, payload, and trailer, exist in various
noncontiguous locations in memory. Scatter gather DMA allows
the segments to be concatenated together by using multiple TDs
in a chain. The chain gathers the data from the multiple locations.
A similar concept applies for the reception of data onto the
device. Certain parts of the received data may need to be
scattered to various locations in memory for software processing
convenience. Each TD in the chain specifies the location for
each discrete element in the chain.
4.3.4.7 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but specif-
ically refers to packet protocols. With these protocols, there may
be separate configuration, data, and status phases associated
with sending or receiving a packet.
For instance, to transmit a packet, a memory mapped configu-
ration register can be written inside a peripheral, specifying the
overall length of the ensuing data phase. The CPU can set up
this configuration information anywhere in system memory and
copy it with a simple TD to the peripheral. After the configuration
phase, a data phase TD (or a series of data phase TDs) can
begin (potentially using scatter gather). When the data phase
TD(s) finish, a status phase TD can be invoked that reads some
memory mapped status information from the peripheral and
copies it to a location in system memory specified by the CPU
for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.3.4.8 Nested DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the appli-
cation. When complete, the second TD calls the first TD, which
again updates the second TD’s configuration. This process
repeats as often as necessary.
PSoC
®
5: CY8C53 Family Data Sheet
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