CY8C5387AXI-108 Cypress Semiconductor Corp, CY8C5387AXI-108 Datasheet - Page 56

• Manufacturer Part Number: CY8C5387AXI-108
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5387AXI-108

• Lead Free Status / Rohs Status: Compliant

9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five
pins (the nTRST pin is optional). The JTAG clock frequency can
be up to 8 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit
transfers, or 1/5 of the CPU clock frequency for 32-bit transfers,
whichever is least. By default, the JTAG pins are enabled on new
devices but the JTAG interface can be disabled, allowing these
pins to be used as General Purpose I/O (GPIO) instead. The
JTAG interface is used for programming the flash memory,
debugging, I/O scan chains, and JTAG device chaining.
9.2 SWD Interface
The SWD interface is the preferred alternative to the JTAG
interface. It requires only two pins instead of the four or five
needed by JTAG. SWD provides all of the programming and
debugging features of JTAG at the same speed. SWD does not
provide access to scan chains or device chaining. The SWD
clock frequency can be up to 1/3 of the CPU clock frequency.
SWD uses two pins, either two of the JTAG pins (TMS and TCK)
or the USBIO D+ and D- pins. The USBIO pins are useful for in
system programming of USB solutions that would otherwise
require a separate programming connector. One pin is used for
the data clock and the other is used for data input and output.
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 µs (key window) after reset, that pin pair
(JTAG or USB) receives a predetermined sequence of 1s and 0s.
SWD is used for debugging or for programming the flash
memory.
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
9.3 Debug Features
The CY8C53 supports the following debug features:
Document Number: 001-55035 Rev. *F
Halt and single-step the CPU
View and change CPU and peripheral registers, and RAM
addresses
Six program address breakpoints and two literal access break-
points
Data watchpoint events to CPU
Patch and remap instruction from flash to SRAM
Debugging at the full speed of the CPU
Debug operations are possible while the device is reset, or in
low power modes
Compatible with PSoC Creator and MiniProg3 programmer and
debugger
Standard JTAG programming and debugging interfaces make
CY8C53 compatible with other popular third-party tools (for
example, ARM / Keil)
PRELIMINARY
9.4 Trace Features
The following trace features are supported:
9.5 SWV and TRACEPORT Interfaces
The SWV and TRACEPORT interfaces provide trace data to a
debug host via the Cypress MiniProg3 or an external trace port
analyzer. The 5 pin TRACEPORT is used for rapid transmission
of large trace streams. The single pin SWV mode is used to
minimize the number of trace pins. SWV is shared with a JTAG
pin. If debugging and tracing are done at the same time then
SWD may be used with either SWV or TRACEPORT, or JTAG
may be used with TRACEPORT, as shown in
Table 9-1. Debug Configurations
9.6 Programming Features
The JTAG and SWD interfaces provide full programming
support. The entire device can be erased, programmed, and
verified. Designers can increase flash protection levels to protect
firmware IP. Flash protection can only be reset after a full device
erase. Individual flash blocks can be erased, programmed, and
verified, if block security settings permit.
9.7 Device Security
PSoC 5 offers an advanced security feature called device
security, which permanently disables all test, programming, and
debug ports, protecting your application from external access.
The device security is activated by programming a 32-bit key
(0x50536F43) to a Write Once Latch (WOL).
All debug and trace disabled
JTAG
SWD
SWV
TRACEPORT
JTAG + TRACEPORT
SWD + SWV
SWD + TRACEPORT
Instruction trace
Data watchpoint on access to data address, address range, or
data value
Trace trigger on data watchpoint
Debug exception trigger
Code profiling
Counters for measuring clock cycles, folded instructions,
load/store operations, sleep cycles, cycles per instruction,
interrupt overhead
Interrupt events trace
Software event monitoring, “printf-style” debugging
PSoC
Debug and Trace Configuration
®
5: CY8C53 Family Data Sheet
GPIO Pins Used
Table
9 or 10
4 or 5
0
2
1
5
3
7
9-1.
Page 56 of 97
[+] Feedback