CY8C5387AXI-108 Cypress Semiconductor Corp, CY8C5387AXI-108 Datasheet - Page 8

• Manufacturer Part Number: CY8C5387AXI-108
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5387AXI-108

• Lead Free Status / Rohs Status: Compliant

Figure 2-3
example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a 2-layer board.
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in
Document Number: 001-55035 Rev. *F
The two pins labeled Vddd must be connected together.
The two pins labeled Vccd must be connected together, with
capacitance added, as shown in
Figure
and
Figure 2-4
2-4.
Vssd
Figure 2-3. Example Schematic for 100-Pin TQFP Part with Power Connections
show an example schematic and an
Vssd
Figure 2-3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Vddd
Vssd
C6
0.1uF
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], nTRST
C12
0.1uF
Vddd
Vssd
and
PRELIMINARY
Power System
Vddd
Vssd
C16
0.1uF
C1
1uF
Vssd
Vddd
C2
0.1uF
Vssd
C15
1uF
on page 23. The trace between the two Vccd pins should be
as short as possible.
The two pins labeled Vssd must be connected together.
PSoC
Vccd
Vssa
10uF, 6.3V
C13
OA0-, REF0, P0[3]
kHzXout, P15[2]
kHzXin, P15[3]
OA0out, P0[1]
OA2out, P0[0]
OA3out, P3[7]
OA1out, P3[6]
®
OA0+, P0[2]
SIO, P12[3]
SIO, P12[2]
SIO, P12[1]
SIO, P12[0]
Vssa
5: CY8C53 Family Data Sheet
Vddio0
C14
U2
0.1uF
CY8C55xx
P4[1]
P4[0]
Vdda
Vssd
Vcca
Vssa
NC
NC
NC
NC
NC
NC
Vddd
Vssd
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
C11
0.1uF
Vssd
Vdda
Vssa
Vcca
Vddd
Vssd
C8
0.1uF
C9
1uF
Vssd
Vssa
Vdda
Vdda
Vssa
C17
C10
1uF
0.1uF
Page 8 of 97
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