MT48H4M16LFB4-75 Micron Technology Inc, MT48H4M16LFB4-75 Datasheet - Page 11
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MT48H4M16LFB4-75
Manufacturer Part Number
MT48H4M16LFB4-75
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48H4M16LFB4-75.pdf
(64 pages)
Specifications of MT48H4M16LFB4-75
Organization
4Mx16
Density
64Mb
Address Bus
14b
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
50mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48H4M16LFB4-75 IT:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT48H4M16LFB4-75 IT:H TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT48H4M16LFB4-75:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48H4M16LFB4-75:H
Manufacturer:
MICRON
Quantity:
20 000
Company:
Part Number:
MT48H4M16LFB4-75:H TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT48H4M16LFB4-75IT:H
Manufacturer:
ISSI
Quantity:
171
Figure 4:
Burst Type
PDF: 09005aef8237ed98, Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN
Mode Register Definition
Note:
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 4.
to prevent Extended
** BA1, BA0 = “0, 0”
Mode Register.
The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block.
to ensure compatibility
with future devices.
Reserved**
*Should program
13
M13
BA1
M10 = “0, 0”
12
M12
BA0
Reserved* WB
11
M11
A11
10
M10
A10
M9
0
1
9
M9
A9
Op Mode
M8
8
A8
7
M7 M6
A7 A6
Programmed Burst Length
M8
11
0
Single Location Access
-
CAS Latency
6
Write Burst Mode
5
M5
A5
M7
0
-
4
M4
A4
BT
M3
Defined
M6-M0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
1
3
M3
A3
-
M2
M6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
M2 M1
M5
A2
M1
64Mb: 4 Meg x 16 Mobile SDRAM
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
M0
A0
Reserved
Reserved
Reserved
Reserved
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
CAS Latency
Address Bus
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
©2006 Micron Technology, Inc. All rights reserved.