MT48H4M16LFB4-75 Micron Technology Inc, MT48H4M16LFB4-75 Datasheet - Page 39

• Manufacturer Part Number: MT48H4M16LFB4-75
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H4M16LFB4-75

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef8237ed98, Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command
9. Burst in bank n continues as initiated.
represented by the current state only.
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
when its burst has been interrupted by bank m’s burst.
charge), the READ to bank m will interrupt the READ on bank n, CAS latency later
(Figure 10 on page 21).
charge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 12
on page 23 and Figure 13 on page 23). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 20
on page 27), with the data-out appearing CAS latency later. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m.
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered
(Figure 18 on page 26). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 27 on
page 32). The PRECHARGE to bank n will begin when the READ to bank m is registered.
the WRITE to bank m will interrupt the READ on bank n when registered (Figure 28 on
page 33). DQM should be used two clocks prior to the WRITE command to prevent bus con-
tention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered.
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CAS latency later (Figure 29 on page 34). The PRECHARGE to bank n will begin
after
WRITE bank n will be data-in registered one clock prior to the READ to bank m.
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after
istered (Figure 30 on page 34). The last valid WRITE to bank n will be data registered one
clock to the WRITE to bank m.
t
WR is met, where
t
WR begins when the READ to bank m is registered. The last valid
t
WR is met, where
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: 4 Meg x 16 Mobile SDRAM
t
WR begins when the WRITE to bank m is reg-
©2006 Micron Technology, Inc. All rights reserved.