MT48H4M16LFB4-75 Micron Technology Inc, MT48H4M16LFB4-75 Datasheet - Page 18

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MT48H4M16LFB4-75

Manufacturer Part Number
MT48H4M16LFB4-75
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48H4M16LFB4-75

Organization
4Mx16
Density
64Mb
Address Bus
14b
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
50mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

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171
Deep Power-Down
PDF: 09005aef8237ed98, Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands should be issued at
once and then every 15.625µs or less, as both SELF REFRESH and AUTO REFRESH
utilize the row refresh counter.
The operating mode deep power-down achieves maximum power reduction by elimi-
nating the power of the whole memory array of the device. Array data will not be
retained once the device enters deep power-down mode.
This mode is entered by having all banks idle then CS# and WE# held LOW with RAS#
and CAS# held HIGH at the rising edge of the clock, while CKE is LOW. This mode is
exited by asserting CKE HIGH.
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: 4 Meg x 16 Mobile SDRAM
t
XSR because time is
©2006 Micron Technology, Inc. All rights reserved.

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