PEB20570FV31XP Lantiq, PEB20570FV31XP Datasheet - Page 142

• Manufacturer Part Number: PEB20570FV31XP
• Manufacturer: Lantiq

Specifications of PEB20570FV31XP

• Lead Free Status / Rohs Status: Compliant

4.7.7
The following GHDLC features related to HDLC protocol may be selected in HDLC
mode:
• Collision Detection: May be active or inactive (relates only to the transmit direction)
• Flags / Ones Interframe: Flags or Ones are transmitted between each frame and are
• CRC Mode: Two possible settings: 16-bit CRC / No CRC (relates to both the transmit
• Push-Pull / Open drain: In push pull mode a pin may be driven to ‘1’ or ‘0’. When in
The GHDLCU is able to receive ’flags’ as well as ’1’ as ITF. If flags are used as ITF the
DELIC is able to detect ITF-flags with only one ’Zero’ between the ’Ones’ (shared ’0’).
Figure 50
4.7.8
The DELIC-LC has one GHDLC channel with a data rate of up to 2.048 Mbit/s.
Although the DELIC-PB features 4 GHDLC channels, not all channels are available for
each application. If full duplex operation is assumed and if the receive data comes
randomly, it’s recommended to use not more than two channels with 2 Mbit/s or 1
channel with up to 8 Mbit/s.
The reason for this is that the data flow through the µP-interface is limited by the µP-
access time, the maximum number of interrupts supported by the µP and by the DMA-
access time.
Assuming a system with 4 x 2 Mbit/s GHDLC ports this would mean a worst case
interrupt repetition rate of 12.5 µs (i.e. 4 x 32 bytes per direction have to be transmitted
via a 32 byte mailbox). Usually the Operating System wouldn’t allow such a high interrupt
rate. However if the performance requirements can be reduced (e.g. not all channels are
active at the same time or the HDLC packet size is small or the packet rate is low) then
a system with 4 x 2 Mbit/s might be reasonable with the DELIC.
Data rates other than 2.048, 4.096 and 8.192 Mbit/s require an external clock. The
DELIC may be configured to use an external clock for each GHDLC port.
Data Sheet
automatically recognized in receive direction. In transmit direction the GHDLCU can
be programmed for either Interframe.
and receive directions, and only when operating in the HDLC mode).
open drain mode a pin may be driven to ‘0’ or high impedance.
data
GHDLC Protocol Features
GHDLC possible Data Rates for the DELIC-LC/PB
Interframe Time Fill with shared Zero
End Flag
End Flag
ITF = Flag
125
ITF = Flag
Functional Description
Start Flag
PEB 20570
PEB 20571
2003-07-31