PEB20570FV31XP Lantiq, PEB20570FV31XP Datasheet - Page 255

PEB20570FV31XP

Manufacturer Part Number
PEB20570FV31XP
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEB20570FV31XP

Lead Free Status / Rohs Status
Compliant
6.2.11.7 DCL Control Register
DCL Control Register (CDCL)
Reset value: 000B
Note: ’x’ = unused bits, read as 0
.
DCLEN
DCL(2:0) DCL Clock Rate
Data Sheet
15
7
x
x
DCL Clock Enable
0 =
1 =
000 =
001 =
010 =
011 =
100 =
H
14
6
x
x
DCL is disabled
DCL is enabled (default)
384 kHz
768 kHz
1536 kHz
2048 kHz (default)
4096 kHz
13
5
x
x
12
4
read/write
x
x
238
DCLEN
11
3
x
10
2
x
Register Description
DCL(2:0)
Address: D086
9
x
1
PEB 20570
PEB 20571
2003-07-31
8
0
x
H

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