PNX1701EH,557 NXP Semiconductors, PNX1701EH,557 Datasheet - Page 452
PNX1701EH,557
Manufacturer Part Number
PNX1701EH,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1701EH557.pdf
(832 pages)
Specifications of PNX1701EH,557
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
Table 10: Video Input Processor (VIP) 1 Registers
PNX17XX_SER_1
Preliminary data sheet
Operating Mode Control Registers
Offset 0x10 6000
31:30
29
28
27:26
25
24
23:22
21
20:18
17
16
15
Bit
Symbol
VID_CFEN[1:0]
VID_OSM
VID_FSEQ
AUX_CFEN[1:0]
AUX_OSM
AUX_FSEQ
AUX_ANC[1:0]
AUX_RAW
reserved
RST_ON_ERR
SOFT_RESET
reserved
3.2 Register Table
VIP Mode Control
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
0
0
0
0
0
0
0
0
0
0
Value
Rev. 1 — 17 March 2006
Description
Video window capture field enable
00 = capture disabled
01 = capture odd only
10 = capture even only
11 = capture both
Video capture one shot mode
0 = continuously capture fields selected by CFEN
1 = capture fields selected by CFEN only once
video capture field sequence
0 = capture fields starting with any field
1 = capture fields starting with odd field
setting has no effect unless VID_CFEN is set to capture both
Auxiliary window capture enable
00 = capture disabled
01 = capture odd only
10 = capture even only
11 = capture both
Auxiliary capture one shot mode
0 = when auxiliary wrap event is reached, buffer wraps around
1 = when auxiliary wrap event is reached, capturing stops
Auxiliary capture field sequence
0 = capture fields starting with any field
1 = capture fields starting with odd field
setting has no effect unless AUX_CFEN is set to capture both
ANC data capture enable
00 = no ANC data captured
01 = odd ANC field blocks. (masked DATA_ID_0 bit matched)
10 = even ANC field blocks. (masked DATA_ID_1 bit matched)
11 = odd/even ANC field blocks. (masked DATA_ID_* bit matched)
Auxiliary raw capture enable
0 = raw capture disabled
1 = raw capture enabled, all samples will be captured
when enabled, AUX_ANC and AUX_CFEN settings are ignored
Reset on error
Writing a one into this bit will automatically reset the block in case of
a pipeline error (e.g. illegal scaling ratio / FIFO overflow)
Soft reset
Writing a one into this bit will reset the block
Chapter 12: Video Input Processor
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
12-21
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