MT46H32M16LFCK-10 Micron Technology Inc, MT46H32M16LFCK-10 Datasheet
MT46H32M16LFCK-10
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MT46H32M16LFCK-10 Summary of contents
Page 1
... A0–A8 PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_1.fm - Rev. F 09/05 EN ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron 512Mb: x16, x32 Mobile DDR SDRAM www.micron.com/mobile Table 2: Speed Grade ...
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... Deep Power-Down (DPD .48 Electrical Specifications .55 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Timing Diagrams .67 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_TOC.fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 ©2005 Micron Technology, Inc. All rights reserved. Advance Table of Contents ...
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... Figure 47: Bank Write – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Figure 48: Write – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Figure 49: 60-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Figure 50: 90-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_LOF.fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM RRD) MIN When 2 < RCD ( RRD) MIN DQSQ, QH, and Data Valid Window (x16 .67 ...
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... Target Normal Output Drive Characteristics (Full-Drive Strength .65 Table 19: Target Reduced Output Drive Characteristics (One-Half Drive Strength .66 PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_LOT.fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2005 Micron Technology, Inc. All rights reserved. Advance ...
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... I/O balls. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the Mobile DDR SDRAM dur- ing READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs ...
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... READ or WRITE command are used to select the bank and the starting column location for the burst access. The Mobile DDR SDRAM provides for programmable READ or WRITE burst lengths continuous page. An AUTO-PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access ...
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... EXTENDED MODE ROW- REGISTER ADDRESS MUX A0–A12, ADDRESS 15 BA0, BA1 REGISTER 2 9 PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM BANK3 BANK2 BANK1 BANK 0 13 ROW- BANK0 ADDRESS MEMORY 8192 LATCH ARRAY & (8,192 x 256 x 64) DECODER 64 ...
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... EXTENDED MODE REGISTER ROW- ADDRESS MUX A0–A12, ADDRESS 15 BA0, BA1 REGISTER 2 10 PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM BANK3 BANK2 BANK1 BANK0 13 ROW- BANK0 ADDRESS MEMORY 8192 LATCH ARRAY & (8,192 x 512 x 32) DECODER 32 SENSE AMPLIFIERS ...
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... Figure 4: 60-Ball VFBGA Assignment PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM DQ15 DQ13 DQ14 DQ11 DQ12 SS Q DQ9 DQ10 UDQS DQ8 SS V UDM NC SS CKE CK CK# A9 A11 A12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... VFBGA Ball Assignment – 10mm x 13mm (Top View CKE PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM DQ31 DQ29 DQ30 DQ17 Q DQ27 DQ28 DQ19 Q DQ25 DQ26 DQ21 Q DQS3 DQ24 DQ23 DM3 NC A13/ CK# A11 A12 A7 A8 A10/AP DM1 A5 Q ...
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... SS F3 PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Type Input Clock the system clock input. CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Input and output data is referenced to the crossing of CK and CK# (both directions of the crossing) ...
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... Q DD L9, M1, N9, P1, R7 PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Type Input Clock the system clock input. CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Input and output data is referenced to the crossing of CK and CK# (both directions of the crossing) ...
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... V A9, F1 A1, F9 PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Type Supply DQ Ground: Isolated on the die for improved noise immunity. Supply Power Supply: +1.8V ±0.1V. Supply Ground. – No Connect: F3 may be left unconnected. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... The double data rate architecture is essentially a 2n-prefetch architec- ture, with an interface designed to transfer two data words per clock cycle at the I/O balls. Single read or write access for the 512Mb Mobile DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corre- sponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls. Read and write accesses to the Mobile DDR SDRAM are burst oriented ...
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... Note that the sequence in which the standard and extended mode registers are programmed is not critical. 10. Issue NOP or DESELECT commands for at least 11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command. Register Definition Mode Registers The mode registers are used to define the specific mode of operation of the Mobile DDR SDRAM ...
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... M12 M11 M10 – Notes: 1. BA1 and BA0 must be “1, 0” to select the extended mode register (vs. the standard mode register). PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM t AC). For the READ command is registered at A12 A11 A10 A9 A8 ...
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... Table 5: Burst Definition Burst Length Continuous page PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Order of Accesses within a Burst Starting Column Address Type = Sequential 0 0-1-2 1-2-3 2-3-0 3-0-1 0-1-2-3-4-5-6 1-2-3-4-5-6-7 2-3-4-5-6-7-0 3-4-5-6-7-0-1 4-5-6-7-0-1-2 5-6-7-0-1-2-3 6-7-0-1-2-3-4-5 ...
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... Table 6: CAS Latency Figure 7: CAS Latency CK# CK COMMAND DQS DQ CK# CK COMMAND DQS DQ PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Allowable Operating Clock Frequency (MHz) Speed – 0 ≤ f ≤ 83.3 -75 0 ≤ f ≤ 66.7 - T1n T2 READ NOP ...
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... PASR defaults to full array if the extended mode register is not loaded. Output Driver Strength Because the Mobile DDR SDRAM is designed for use in smaller systems that are typically point-to-point connections, an option to control the drive strength of the output buffers is provided. Drive strength should be selected based on the expected loading of the memory bus. There are four allowable settings for the output drivers— ...
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... Figure 9 on page 21 illustrates the clock stop mode recommended that the Mobile DDR SDRAM precharged state if any changes to the clock frequency are expected. This will eliminate timing violations that may other- wise occur during normal operations. ...
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... Any valid command is allowed, device is not in clock suspend mode. 3. Any DRAM operation already in process must be completed before entering clock stop mode. This includes the DRAM must be either in the idle or precharge state before clock suspend mode can be entered enter and maintain a clock stop mode LOW, CK# = HIGH, CKE = HIGH. ...
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... Name (Function) Write enable Write inhibit Notes: 1. Used to mask write data; provided coincident with the corresponding data. 2. All states and sequences not shown are reserved and/or illegal. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM CS# RAS# CAS# WE ...
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... NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected Mobile DDR SDRAM to perform a NOP . This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode registers are loaded via inputs A0–A12. See mode register descriptions in “ ...
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... AUTO REFRESH command is registered and ends SELF REFRESH The SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the Mobile DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command, except that CKE is disabled (LOW). All com- mand and address input signals except CKE are “ ...
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... As the case temperature of the Mobile DDR SDRAM changes, the oscillation frequency will change to accommodate the change of temperature. This happens because the DRAM capacitors lose charge faster at higher temperatures. To ensure efficient power dissipation during self refresh, the oscil- lator will change to refresh at the slowest rate possible to maintain data integrity ...
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... Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the Mobile DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 10. ...
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... CK and CK#). Figure 13 on page 29 shows general timing for each possi- ble CAS latency setting. DQS is driven by the Mobile DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coinci- dent with the last data-out element is known as the read postamble ...
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... BA0 Column Address BA = Bank Address Enable Auto Precharge DIS AP = Disable Auto Precharge PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM HIGH DIS AP BA DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Figure 13: READ Burst CK# CK COMMAND ADDRESS DQS DQ CK# CK COMMAND ADDRESS DQS DQ Notes OUT Shown with nominal PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T0 T1 T1n T2 READ NOP NOP Bank a, Col OUT READ NOP NOP Bank a, Col data-out from column n ...
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... 16, or continuous page (if 4, the bursts are concatenated 16, or continuous page, the second burst interrupts the first). 3. Shown with nominal 4. Example applies only when READ commands are issued to same device. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T0 T1 T1n T2 READ ...
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... 16, or continuous page (if burst is 8, 16, or continuous page, the second burst interrupts the first). 3. Shown with nominal 4. Example applies when READ commands are issued to different devices or nonconsecutive READs. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T0 T1 T1n T2 T2n READ ...
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... Figure 19 on page 35. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until Note: Part of the row precharge time is hidden during the access of the last data elements. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T0 T1 T1n T2 READ ...
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... ADDRESS DQS DQ Notes: 1. Dout n = data-out from column 16, or continuous page. 3. Shown with nominal 4. BST = BURST TERMINATE command; page remains open. 5. CKE = HIGH. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T0 T1 T1n T2 T2n 4 READ BST NOP Bank a, ...
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... the cases shown (applies for bursts of 8, 16, or continuous page as well the BST command shown can be a NOP). 4. Shown with nominal 5. 5. BST = BURST TERMINATE command; page remains open CKE = HIGH. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T0 T1 T1n T2 5 READ ...
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... A READ command with auto precharge enabled, provided a precharge to be performed at x number of clock cycles after the READ command, where PRE = PRECHARGE command; ACT = ACTIVE command. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T0 T1 T1n T2 5 READ ...
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... DM, as shown in Figure 26 on page 41 and Figure 30 on page 45. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM t t DQSS [MIN] and DQSS [MAX]) might not be intuitive, they have also ...
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... BA0 Column Address BA = Bank Address Enable Auto Precharge DIS AP = Disable Auto Precharge PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM HIGH DIS AP BA DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... ADDRESS t DQSS (NOM) DQS DQ DM Notes (n) = data-in for column b (n uninterrupted burst shown. 3. Each W RITE command may be to any bank. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T2n WRITE NOP NOP Bank a, Col b t DQSS t DQSS ...
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... ( the next data-in following D grammed burst order. 3. Programmed 16, or continuous page in cases shown. 4. Each WRITE command may be to any bank. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T0 T1 T1n T2 T2n WRITE NOP NOP ...
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... The READ and WRITE commands are to same device. However, the READ and WRITE com- mands may be to different devices, in which case mand could be applied earlier. 5. A10 is LOW with the WRITE command (auto precharge is disabled). PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T1 T1n T2 T2n T3 ...
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... DQS is required at T2 and T2n (nominal case) to register DM the burst was used, DM and DQS would be required at T3 and T3n because the READ command would not mask these two data elements. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T1 T1n T2 T2n ...
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... DQS is required at T2 and T2n (nominal case) to register DM the burst was used, DM and DQS would be required at T3 and T3n because the READ command would not mask these two data elements. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T1 T1n T2 T2n ...
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... The READ and WRITE commands are to same device. However, the READ and WRITE com- mands may be to different devices, in which case mand could be applied earlier. 5. A10 is LOW with the WRITE command (auto precharge is disabled). 6. PRE = PRECHARGE command. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T1 T1n T2 T2n T3 NOP ...
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... The READ and WRITE commands are to same device. However, the READ and WRITE com- mands may be to different devices, in which case mand could be applied earlier. 5. A10 is LOW with the WRITE command (auto precharge is disabled). 6. PRE = PRECHARGE command. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T1n T2 T2n T3 T3n NOP ...
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... The READ and WRITE commands are to same device. However, the READ and WRITE com- mands may be to different devices, in which case mand could be applied earlier. 5. A10 is LOW with the WRITE command (auto precharge is disabled). 6. PRE = PRECHARGE command. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T1 T1n T2 T2n T3 T3n ...
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... Single = Only bank selected by BA1 and BA0 will be precharged. Power-Down (CKE Not Active) Unlike SDR SDRAMs, Mobile DDR SDRAMs require CKE to be active at all times when an access is in progress: from the issuing of a READ or WRITE command until completion of the burst; thus a clock suspend is not supported. For READs, a burst completion is defined when the read postamble is satisfied ...
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... The power-down duration is limited by the refresh requirements of the device. While in power-down, CKE LOW must be maintained at the inputs of the Mobile DDR SDRAM, while all other input signals are “Don’t Care.” The power-down state is synchro- nously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command) ...
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... Data will not be retained once the device enters deep power-down mode. Before entering DPD mode the DRAM must be in all banks idle state with no activity on the data bus ( with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW. CKE must be held LOW to maintain DPD mode ...
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... Notes: 1. Clock must be stable prior to CKE going HIGH. 2. DPM = Deep power-down mode command; PRE ALL = Precharge all banks. 3. Upon exit of deep power-down mode, a PRECHARGE ALL command must be issued fol- lowed by the initialization sequence (page 14). PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Ta0 ( ...
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... All banks idle Notes: 1. CKE edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMAND MAND 4. All states and sequences not shown are illegal or reserved CKE pertains. 6. DESELECT or NOP commands should be issued on any clock edges occurring during the period ...
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... NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when t Once RC is met, the DDR SDRAM will be in the all banks idle state. Accessing Mode PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM CAS# ...
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... BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM t MRD is met, the Mobile DDR SDRAM will be in the all banks Micron Technology, Inc., reserves the right to change products or specifications without notice. 52 Advance Deep Power-Down (DPD) t ...
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... PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when auto precharge was disabled. The access period starts with registration of the com- mand and ends where the precharge period (or PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM CAS# WE# Command/Action X X ...
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... A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com- mand. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM To Command READ or READ w/AP WRITE or WRITE w/AP PRECHARGE ...
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... Input leakage current Any input 0V ≤ V ≤ (All other pins not under test = 0V) Output leakage current (DQs are disabled; 0V ≤ V ≤ V OUT DD PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Symbol IT T STG Q = +1.8V ±0.1V) Symbol 0.8 × V ...
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... Address and control inputs are switching; Data bus inputs are stable Operating burst read: t One bank active bursts 0mA; Address inputs are switching; 50% data OUT changing each burst PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Symbol ...
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... CK (MIN); Address and control inputs are stable; Data bus inputs are stable Deep power-down current Address and control balls are stable; Data bus inputs are stable PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM = +1.8V ±0.1V Symbol ...
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... CK (MIN); continuous WRITE bursts; Address inputs are switching; 50% data changing each burst Auto refresh: Burst refresh; CKE = HIGH Address and control inputs are switching; Data bus inputs are stable PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM = +1.8V ±0.1V Symbol ...
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... Address and control inputs are stable; Data bus inputs are stable Deep power-down current Address and control pins are stable; Data bus inputs are stable PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM = +1.8V ±0.1V Symbol I Full Array, 85° Full Array, 70° ...
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... Address and control input pulse width LOAD MODE REGISTER command cycle time DQ–DQS hold, DQS to first non- valid, per access Data Hold Skew Factor ACTIVE-to-PRECHARGE command PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM = +1.8V ±0.1V -6 Symbol Min Max Min t ...
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... Data valid output window (DVW) Average periodic refresh interval Exit SELF REFRESH to first valid command Exit power-down mode to first valid command t Minimum CKE HIGH/LOW time PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM = +1.8V ±0.1V -6 Symbol Min Max Min ...
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... HZ and tions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM . SS , and electrical AC and DC characteristics may be conducted DD ...
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... Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -150mV or 1.6V, whichever is more positive. 33. Normal Output Drive Curves (notes to be added). PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM RFC) for I ...
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... Must ensure that all data sheet specifications are satisfied. 50. JEDEC-standard option (A12 page size). 51. Reduced page size option (A13). PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Q + 1.0V for a pulse width ≤ 3ns and the pulse width (MAX ...
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... Note: The above characteristics are specified under best and worst process variation/conditions. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 2.80 18.53 5.60 26.80 8.40 32 ...
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... Note: The above characteristics are specified under best and worst process variation/conditions. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 1.27 8.42 2.55 12.30 3.82 14 ...
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... HP is the lesser of 6. The data valid window is derived for each DQS transitions and is defined as 7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM t t DQSQ, QH, and Data Valid Window (x16) ...
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... DQS transition and ends with the last valid DQ transition derived from the lesser of 5. The data valid window is derived for each DQS transition and is PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM t t DQSQ, QH, and Data Valid Window (x32) T2 T2n ...
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... All DQ values, collectively Notes transitioning after DQS transition define 2. All DQ must transition the DQ output window relative to CK, and is the “long term” component of DQ skew. 4. Shown with PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM and DQSCK T3n T2n ...
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... DQS3 controls DQ[31:24]. 6. For x16, LDM controls the lower byte; UDM controls the upper byte. 7. For x32, DMO controls DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls DQ[31:24]. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T1n T2 ...
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... REFRESH command, ACT = ACTIVE command Row Address Bank Address. 2. NOP or DESELECT commands are required for at least 200µs. 3. Other valid commands are possible. 4. NOPs or DESELECTs are required during this time. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T1 Ta0 Tb0 ( ( ...
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... No column accesses are allowed progress at the time power-down is entered. 3. There must be at least one clock pulse during PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T1 T2 Ta0 ( ...
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... DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown. 6. The second AUTO REFRESH is not required and is only shown as an example of two back- to-back AUTO REFRESH commands. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM Ta0 ...
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... Notes: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within specifications by Ta0. 2. Device must be in the all banks idle state prior to entering self refresh mode. 3. NOPs or DESELECT are required for AUTO REFRESH command. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM ...
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... NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. The PRECHARGE command can only be applied Refer to Figure 36 on page 67 and Figure 37 on page 68 for DQS and DQ timing details. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM ...
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... PRE = PRECHARGE, ACT = ACTIVE Row address Bank address. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. Refer to Figure 36 on page 67 and Figure 37 on page 68 for detailed DQS and DQ timing. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM ...
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... PRE = PRECHARGE, ACT = ACTIVE Row address Bank address. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times DSH is applicable during t 8. DSH is applicable during PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T4n ...
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... PRE = PRECHARGE, ACT = ACTIVE Row address Bank address. 5. NOP commands are shown for ease of illustration; other commands may be valid at these times DSH is applicable during t 7. DSH is applicable during PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T4n NOP 5 WRITE 2 NOP 5 ...
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... PRE = PRECHARGE, ACT = ACTIVE Row address Bank address. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times DSH is applicable during t 8. DSH is applicable during PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM T4n NOP 6 WRITE 2 ...
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... L 3.20 10.00 ±0.10 Notes: 1. All dimensions in millimeters. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM 0.65 ±0.05 SOLDER BALL MATERIAL: 62% Sn, 36% Pb 96.5% Sn, 3% Ag, 0.5% Cu SOLDER BALL PAD: Ø0.40 SOLDER MASK DEFINED SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC ...
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... Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Advance: This data sheet contains initial descriptions of products still under development. PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3 MT46H32M16LF_2..fm - Rev. F 09/05 EN 512Mb: x16, x32 Mobile DDR SDRAM 0.65 ±0.05 BALL A1 ID BALL A1 6.50 ±0. 13.00 ± ...