MT46H32M16LFCK-10 Micron Technology Inc, MT46H32M16LFCK-10 Datasheet - Page 5

• Manufacturer Part Number: MT46H32M16LFCK-10
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M16LFCK-10

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 1:
FBGA Part Marking Decoder
General Description
PDF: 09005aef818ff7c5/Source: 09005aef81a6c5f3
MT46H32M16LF_2..fm - Rev. F 09/05 EN
512Mb Mobile DDR Part Numbering
Due to space limitations, FBGA-packaged components have an abbreviated part mark-
ing that is different from the part number. Micron’s FBGA Part Marking Decoder is avail-
able at www.micron.com/decoder.
The 512Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access mem-
ory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. Each
of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1K columns by 16 bits.
Each of the x32’s 134,217,728-bit banks is organized as 8,192 rows by 512 columns by 32
bits.
The 512Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high-
speed operation. The double data rate architecture is essentially a 2n-prefetch architec-
ture with an interface designed to transfer two data words per clock cycle at the I/O
balls. A single read or write access for the 512Mb Mobile DDR SDRAM effectively con-
sists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and
two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the Mobile DDR SDRAM dur-
ing READs and by the memory controller during WRITEs. DQS is edge-aligned with data
for READs and center-aligned with data for WRITEs. The x16 offering has two data
strobes, one for the lower byte and one for the upper byte and the x32 offering has four
data strobes, one per byte.
The 512Mb Mobile DDR SDRAM operates from a differential clock (CK and CK#); the
crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of
CK. Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registration of an ACTIVE command, which
is then followed by a READ or WRITE command. The address bits registered coincident
Example Part Number: MT46H16M32LFXX-75IT
MT46V
V
1.8V/1.8V
DD
/V
DD
Q
V
V
DD
Configuration
DD
16 Meg x 32
Q
/
Package
10 x 11.5 VFBGA (lead-free)
10 x 13 VFBGA (lead-free)
H
Configuration
Mobile
16M32LF
Package
5
-
Speed
-75
-10
-6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x16, x32 Mobile DDR SDRAM
Speed Grade
t
CK = 6.0ns
t
t
CK = 7.5ns
CK = 9.6ns
I T
Temp.
Operating Temp.
Standard
Industrial Temp.
FBGA Part Marking Decoder
©2005 Micron Technology, Inc. All rights reserved.
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