AD6653-150EBZ Analog Devices Inc, AD6653-150EBZ Datasheet
AD6653-150EBZ
Specifications of AD6653-150EBZ
AD6653-150EBZ Summary of contents
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... DATA INTERFACE FD[0:3]B SMI SMI SDFS SCLK/ PDWN Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 IF Diversity Receiver AD6653 DVDD DRVDD AD6653 D11A D0A CLK+ DIVIDE CLK– ADC NCO DUTY DCOA DCO CYCLE GENERATION ...
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... AD6653 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 ADC DC Specifications ............................................................... 5 ADC AC Specifications ............................................................... 6 Digital Specifications ................................................................... 7 Switching Specifications .............................................................. 9 Timing Specifications ................................................................ 10 Absolute Maximum Ratings.......................................................... 13 Thermal Characteristics ............................................................ 13 ESD Caution................................................................................ 13 Pin Configurations and Function Descriptions ......................... 14 Equivalent Circuits ......................................................................... 18 Typical Performance Characteristics ........................................... 19 Theory of Operation ...
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... REVISION HISTORY 11/07—Revision 0: Initial Version Rev Page AD6653 ...
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... Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD6653 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Rev Page ...
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... I currents. AVDD DVDD Rev Page AD6653 AD6653BCPZ-150 Unit Min Typ Max 12 Bits Guaranteed ±0.2 ±0.6 % FSR −5.2 −3.2 −0.9 % FSR ±0.2 ±0.7 % FSR ±0.2 ±0.7 % FSR ±17 ppm/°C ± ...
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... See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 See the Applications Information section for more information about the worst other specifications for the AD6653. 3 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel. ...
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... Full −10 +10 Full 26 Full 2 Full 1.22 3.6 Full 0 0.6 Full −10 +10 Full 38 128 Full 26 Full 5 Rev Page AD6653 AD6653BCPZ-150 Unit Min Typ Max CMOS/LVDS/LVPECL 1 p-p AVDD − 0.3 AVDD + 1.6 V 1.1 V AVDD V 1.2 3 0.8 V −10 +10 μA −10 +10 μ ...
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... Full 1.75 Full 0.2 Full 0.05 Full 250 350 450 Full 1.15 1.25 1.35 Full 150 200 280 Full 1.15 1.25 1.35 Rev Page AD6653BCPZ-150 Unit Min Typ Max 1.22 3 0.6 V −90 −134 μA −10 +10 μA 26 kΩ 3. ...
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... Full 3.7 5.3 Full 38 /8 Full Mix Full 109 S Full 1.0 Full 0.1 Full 350 Full 44 Rev Page AD6653 AD6653BCPZ-150 Unit Max Min Typ Max 625 625 MHz 125 20 150 MSPS 125 10 150 MSPS 6.66 ns 5.6 2.0 3.33 4.66 ns 4.4 3 ...
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... AD6653 TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to the rising edge of CLK setup time SSYNC t SYNC to the rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK ...
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... CHANNEL B: CHANNEL A: CHANNEL B: DATA DATA CHANNEL B: CHANNEL A: CHANNEL DCO t t SSYNC HSYNC Figure 7. SYNC Timing Inputs Rev Page AD6653 t DCO CHANNEL A: CHANNEL B: DATA DATA CHANNEL A: CHANNEL B: FD BITS FD BITS CHANNEL A/B: CHANNEL A/B: Q DATA I DATA CHANNEL A/B: CHANNEL A/B: FD BITS FD BITS ...
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... AD6653 CLK+ CLK– t CSSCLK SMI SCLK SMI SDFS SMI SDO t t SSCLKSDFS SSCLKSDFS Figure 8. Signal Monitor SPORT Output Timing Rev Page DATA DATA ...
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... Rev Page Airflow Velocity (m/s) θ θ 18.8 0.6 1.0 16.5 2.0 15.8 is specified for a 4-layer PCB with a solid ground addition, metal in direct contact with the AD6653 1, 4 θ Unit JB 6.0 °C/W °C/W °C/W ...
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... PIN 1 INDICATOR DRVDD 1 D4B 2 D5B 3 D6B 4 EXPOSED PADDLE, PIN 0 D7B 5 (BOTTOM OF PACKAGE) D8B 6 D9B 7 D10B 8 AD6653 9 PARALLEL CMOS DCOB 10 TOP VIEW DCOA 11 (Not to Scale) DNC 12 DNC 13 14 D1A 15 D2A 16 Figure 9. LFCSP Parallel CMOS Pin Configuration (Top View) Description Digital Output Ground. ...
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... SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select. Active low. Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode. Rev Page AD6653 ...
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... FD3− Output PIN 1 INDICATOR DRVDD 1 DNC 2 DNC 3 4 EXPOSED PADDLE, PIN 0 5 (BOTTOM OF PACKAGE) D1– 6 D1+ 7 D2– 8 AD6653 D2+ 9 PARALLEL LVDS DCO– 10 TOP VIEW DCO+ 11 (Not to Scale) D3– 12 D3+ 13 D4– 14 D4+ 15 D5– 16 Figure 10. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View) Description Digital Output Ground ...
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... SPI Serial Data Input/Output/Duty Cycle Stabilizer in External Pin Mode. SPI Chip Select. Active low. Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input (Active High) in External Pin Mode. Rev Page AD6653 ...
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... AD6653 EQUIVALENT CIRCUITS VIN Figure 11. Equivalent Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 12. Equivalent Clock lnput Circuit DRVDD DRGND Figure 13. Equivalent Digital Output Circuit DRVDD DRVDD 26kΩ 1kΩ SDIO/DCS Figure 14. Equivalent SDIO/DCS Circuit or SMI SDFS Circuit SCLK/DFS Figure 15 ...
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... NCO enabled, FIR filter enabled, unless otherwise noted. In the FFT plots that follow, = 18.75MHz 2.4 MHz 18.75 MHz Figure 22. AD6653-150 Single-Tone FFT with f NCO 30.3 MHz MHz Figure 23. AD6653-150 Single-Tone FFT with f IN NCO 70.1 MHz MHz IN NCO Rev Page 150MSPS 140.1MHz @ –1dBFS SNR = 70.6dBc (71.6dBFS) – ...
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... Figure 27. AD6653-125 Single-Tone FFT with 445.1 MHz 429 MHz Figure 28. AD6653-125 Single-Tone FFT with f NCO = 15.75MHz 2.4 MHz 15.75 MHz Figure 29. AD6653-125 Single-Tone FFT with f NCO THIRD HARMONIC 30.3 MHz MHz Figure 30. AD6653-125 Single-Tone FFT with f IN NCO Rev Page 125MSPS 70.3MHz @ – ...
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... REFERENCE LINE –3.5 –4.0 –30 –20 – with IN SFDR = +25°C 300 350 400 450 ) and Figure 36. AD6653-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN Rev Page SFDR = +85°C 85 SFDR = +25°C 80 SFDR = –40° SNR = +25°C SNR = +85°C 65 SNR = –40° ...
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... IN = 177 MHz NCO –20 –40 –60 –80 –100 –120 170 MHz 32.12 MHz, Figure 42. AD6653-150 Single-Tone SNR/SFDR vs. Sample Rate (f IN2 Rev Page 150MSPS 169.12MHz @ –7dBFS 172.12MHz @ –7dBFS –20 SFDR = 83.6dBc (90.6dBFS 177MHz NCO –40 –60 – FREQUENCY (MHz) Figure 40 ...
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... DUTY CYCLE (%) Figure 44. AD6653-150 SNR/SFDR vs. Duty Cycle with MHz NCO 90 0.21 LSB rms 0.2 Figure 45. AD6653-150 SNR/SFDR vs. Input Common Mode (VCM) with 30.3 MHz, IN Rev Page AD6653 SFDR SNR 0.4 0.6 0.8 1.0 1.2 1.4 INPUT COMMON-MODE VOLTAGE ( 30.3 MHz, f ...
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... ADC core. The output common mode of the reference buffer is set to VCMREF (approximately 1.6 V). Input Common Mode The analog inputs of the AD6653 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that V recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 45) ...
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... ADC. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD6653 (see Figure 47), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...
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... Figure 51. Single-Ended Input Configuration VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD6653. The input range can be adjusted by varying the reference voltage applied to the AD6653, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly ...
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... Jitter Considerations section. Figure 57 and Figure 58 show two preferred methods for clocking the AD6653 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal, using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6653 to approximately 0 ...
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... Figure 62. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS) Input Clock Divider The AD6653 contains an input clock divider with the ability to divide the input clock by integer values between 1 and divide ratio other than 1 is selected, the duty cycle stabilizer is automatically enabled. ...
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... Figure 63. SNR vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD6653. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise ...
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... The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD6653. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD6653 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance may degrade. Data Clock Output (DCO) ...
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... HALF-BAND DECIMATING FILTER AND FIR FILTER The goal of the AD6653 digital filter block is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest. The half-band filter is designed to operate ...
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... This processing stage comprises a digital tuner consisting of a 32-bit complex numerically controlled oscillator (NCO). The two channels of the AD6653 share a single NCO. The NCO is optional and can be bypassed by clearing Bit 0 of Register 0x11D. This NCO block accepts a real input from the ADC stage and outputs a frequency translated complex (I and Q) output ...
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... DECIMATING HALF-BAND FILTER AND FIR FILTER The goal of the AD6653 half-band digital filter is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest. This filter is designed to operate as either a low-pass or a high-pass filter and to provide >100 dB of alias protection for 11% of the input rate of the structure ...
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... The final NCO provides a −161248 means to move this complex output signal away from dc so that 337056 a real output can be provided from the AD6653. The final NCO, 922060 if enabled, translates the output from frequency equal to the ADC sampling frequency divided ...
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... FAST DETECT OVERVIEW The AD6653 contains circuitry to facilitate fast overrange detection, allowing very flexible external gain control imple- mentations. Each ADC has four fast detect (FD) output pins that are used to output information about the current state of the ADC input level ...
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... ADC clock cycles. An overrange at the input is indicated by this bit 12 clock cycles after it occurs. GAIN SWITCHING The AD6653 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging converters are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed ...
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... The operation of the increment gain output and decrement gain output is shown graphically in Figure 73. DWELL TIME TIMER RESET BY RISE ABOVE F_LT Figure 73. Threshold Settings for C_UT, F_UT, F_LT, DG, and IG Rev Page UPPER THRESHOLD (COARSE OR FINE) FINE LOWER THRESHOLD TIMER COMPLETES BEFORE DWELL TIME SIGNAL RISES ABOVE F_LT AD6653 ...
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... AD6653 SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a particular threshold. Together, these functions can be used to ...
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... GSM. Rev Page POWER MONITOR DOWN IS COUNT = 1? PERIOD REGISTER COUNTER LOAD CLEAR LOAD POWER MONITOR A COMPARE COMPARE HOLDING A>B A>B REGISTER B UPPER THRESHOLD REGISTER Figure 76. ADC Input Threshold Crossing Block Diagram AD6653 TO INTERRUPT CONTROLLER TO MEMORY MAP ...
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... Bits[5:2] of Register 0x10C (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD6653 ADC sample rate in hertz (Hz). CLK DC Correction Readback The current dc correction value can be read back in Register 0x10D and Register 0x10E for Channel A and Register 0x10F and Register 0x110 for Channel B ...
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... CHANNEL/CHIP SYNCHRONIZATION The AD6653 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider, NCO, half-band filters, and signal monitor block can be synchronized using the SYNC input ...
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... The pins described in Table 22 comprise the physical interface between the user programming device and the serial port of the AD6653. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. ...
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... Table 24 provides a brief description of the general features that are accessible via the SPI. These features are described in Application Note AN-877, Interfacing to High Speed ADCs via SPI (see www.analog.com). The AD6653 part-specific features are described in the Memory Map Register Description section. Table 24. Features Accessible Using the SPI ...
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... Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD6653 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 25. Logic Levels An explanation of logic level terminology follows: • ...
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... Open (Global) 0x0B Clock Divide Open Open (Global) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit Chip ID[7:0] (AD6653 = 0x0E) (default) Speed Grade ID[4:3] Open Open 00 = 150 MSPS 01 = 125 MSPS Open Open Open Open Open Open Open Open External ...
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... AD6653 Addr. Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0D Test Mode Open Open (Local) 0x10 Offset Open Open Adjust (Local) 0x14 Output Mode Drive Output strength type 3 CMOS CMOS LVDS ANSI (global) LVDS 1.8 V CMOS or reduced LVDS (global) 0x16 Clock Phase ...
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... Open Open Signal Signal monitor mode monitor 00 = rms/ms magnitude rms/ peak detector select 10 = threshold crossing 0 = rms 11 = threshold crossing Rev Page AD6653 Default Default Bit 0 Value Notes/ Bit 1 (Hex) Comments (LSB) 0x00 0x00 0x00 0x00 0x00 0x00 In ADC clock ...
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... AD6653 Addr. Register Bit 7 Bit 6 (Hex) Name (MSB) 0x113 Signal Monitor Period Register 0 (Global) 0x114 Signal Monitor Period Register 1 (Global) 0x115 Signal Monitor Period Register 2 (Global) 0x116 Signal Monitor Value Channel A Register 0 (Global) 0x117 Signal Monitor Value Channel A Register 1 (Global) 0x118 ...
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... Bit 2 enables the spectral reversal feature of the half-band filter. Bit 1—High-Pass/Low-Pass Select Bit 1 enables the high-pass mode of the half-band filter when set high. Setting this bit low enables the low-pass mode (default). Bit 0—Reserved Bit 0 reads back Rev Page AD6653 /8 output mix output mix. This sync is S ...
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... Bits[5:2] of Register 0x10C (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD6653 ADC sample rate in hertz (Hz). CLK Bit 1—DC Correction for Signal Path Enable Setting this bit high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path ...
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... When Bit 1 is cleared, amplitude dither is disabled. Bit 0—NCO32 Enable When Bit 0 is set, this bit enables the 32-bit NCO operating at the frequency programmed into the NCO frequency register. When Bit 0 is cleared, the NCO is bypassed and shuts down for power savings. Rev Page AD6653 ...
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... NCO_FREQ is a 32-bit twos complement number representing the NCO frequency register the desired carrier frequency in hertz (Hz the AD6653 ADC clock rate in hertz (Hz). CLK NCO Phase Offset (Register 0x122 and Register 0x123) Register 0x122, Bits[7:0]—NCO Phase Value[7:0] Register 0x123, Bits[7:0]—NCO Phase Value[15:8] ...
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... DRVDD current can be higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage to the AD6653, but it should be taken into account when consid- ering the maximum DRVDD current for the part. Rev Page ...
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... The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 48. RBIAS The AD6653 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. ...
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... EVALUATION BOARD The AD6653 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configura- tions. The converter can be driven differentially through a double balun configuration (default) or optionally through the AD8352 differential driver. The ADC can also be driven in a single-ended fashion ...
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... The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. When the AD6653 input clock divider is utilized, clock frequencies up to 625 MHz can be input into the evaluation board through Connector S5. ...
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... Populate the optional amplifier output path with the desired components including an optional low-pass filter. Install 0 Ω resistors, R44 and R48. R43 and R47 should be increased (typically to 100 Ω) to increase to 200 Ω the output impedance seen by the AD8352. Rev Page AD6653 ...
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... AD6653 SCHEMATICS M OH 10K R41 M OH R29 M OH 100 R127 4.12K R126 P DN R36 24 24.9 R35 F Figure 83. Evaluation Board Schematic, Channel A Analog Inputs Rev Page 06708-090 R43 R47 57 57.6 R1 R28 2 2 ...
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... R53 AMPVDD 100OHM R129 K 4.12 R128 DNP R68 24.9OHM 24.9OHM R134 R135 F Figure 84. Evaluation Board Schematic, Channel B Analog Inputs Rev Page 06708-091 57.6OHM R72 33OHM 33OHM R70 R71 OHM 0 F R69 F 57.6OHM 57.6OHM R52 R51 2 2 AD6653 ...
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... AD6653 10KOHM 10KOHM R85 24.9OHM R83 F R82 OHM 0 R8 57.6OHM R30 2 Figure 85. Evaluation Board Schematic, DUT Clock Input Rev Page 06708-092 TP2 1 2 DNP R34 57.6OHM R7 2 ...
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... Figure 86. Evaluation Board Schematic, Optional AD9516 Clock Circuit Rev Page 06708-093 2 2 PAD 2 VS_OUT89_ 32 1 VS_OUT89_ 31 V VS_OUT45_DI 30 OUT5B 29 OUT5 28 V VS_OUT45_DR R VS_OUT_D 27 OUT4B 26 OUT4 25 PDB PDB 24 B RESET B RESET 23 SDIO SDI 22 SDO SDO 21 NC4 20 NC3 19 NC2 18 CSB 2 CSB_ 49.9 R89 2 AD6653 ...
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... AD6653 A C Figure 87. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input 2 RES040 10KOHM R105 2 RES040 10KOHM R103 2 RES040 10KOHM R102 2 RES040 10KOHM R100 2 RES040 10KOHM R107 2 RES040 10KOHM R106 24.9OHM R87 TP1 1 3 RES060 57.6OHM R45 2 Rev Page 06708-094 ...
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... FD1 FD1A FD2 FD3 FD2A 4 13 PWR_SD PWR_SCL FD3A PWR_SDF RES040 OHM 0 R112 Figure 88. Evaluation Board Schematic, DUT 64 DRGND 63 D3B 62 D2B 61 D1B 60 D0B_LSB DVDD2 56 FD3B 55 FD2B 54 FD1B 53 FD0B 52 SYNC SYNC 51 SPI_CSB 50 CLK- 49 CLK+ Rev Page AD6653 06708-095 DVDD SPI_CSB - CLK + CLK ...
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... AD6653 10KOHM R118 2 RES040 VAL R130 2 RES040 10KOHM R140 Figure 89. Evaluation Board Schematic, Digital Output Interface Rev Page 06708-096 100OHM R77 ...
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... Figure 90. Evaluation Board Schematic, SPI Circuitry Rev Page AD6653 06708-097 2 RES040 10KOHM R65 ...
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... AD6653 GND RES060 261OHM A C R16 CR7 2 1 S2A_REC T 76.8KOHM M 147KOH R13 R14 SJ35 Figure 91. Evaluation Board Schematic, Power Supply Rev Page 06708-098 1 TP25 ...
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... GND 4 1 SJ37 SJ36 GND GND Figure 92. Evaluation Board Schematic, Power Supply (Continued) Rev Page 06708-099 M 140KOH M 78.7KOH R25 R15 AD6653 ...
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... AD6653 EVALUATION BOARD LAYOUTS Figure 93. Evaluation Board Layout, Primary Side Rev Page ...
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... Figure 94. Evaluation Board Layout, Ground Plane Rev Page AD6653 ...
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... AD6653 Figure 95. Evaluation Board Layout, Power Plane Rev Page ...
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... Figure 96. Evaluation Board Layout, Power Plane Rev Page AD6653 ...
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... AD6653 Figure 97. Evaluation Board Layout, Ground Plane Rev Page ...
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... Figure 98. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page AD6653 ...
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... AD6653 Figure 99. Evaluation Board Layout, Silkscreen, Primary Side Rev Page ...
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... Figure 100. Evaluation Board Layout, Silkscreen, Secondary Side Rev Page AD6653 ...
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... AD6653 BILL OF MATERIALS Table 26. Evaluation Board Bill of Materials (BOM) Reference Item Qty Designator Description 1 1 AD6653CE_REVB PCB C3, C6, C7, 0.1 μ ceramic C13, C14, C17, C18, capacitor, SMT 0402 C20 to C26, C32, C57 to C61, C65 to C76, C81 to C83, C96 to C101, C103, C105, C107, ...
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... R76 200 Ω, 0402, 1/ resistor 36 4 S2, S3, S5 ,S12 SMA, inline, male, coaxial connector 37 1 SJ35 0 Ω, 1 resistor Balun IC, AD6653 Clock distribution, PLL Dual inverter Dual buffer IC, open-drain circuits UHS dual buffer U15 to U17 16-bit CMOS buffer IC 45 ...
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... TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD6653BCPZ-150 −40°C to +85°C 1 AD6653BCPZ-125 −40°C to +85°C 1 AD6653-125EBZ 1 AD6653-150EBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 BSC BSC SQ 0.50 0. 0.30 0.80 MAX ...
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... NOTES Rev Page AD6653 ...
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... AD6653 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06708-0-11/07(0) Rev Page ...