AD6653-150EBZ Analog Devices Inc, AD6653-150EBZ Datasheet - Page 50

• Manufacturer Part Number: AD6653-150EBZ
• Manufacturer: Analog Devices Inc

Specifications of AD6653-150EBZ

• Lead Free Status / Rohs Status: Compliant

AD6653
Fast Detect Control (Register 0x104)
Bits[7:4]—Reserved
Bits[3:1]—Fast Detect Mode Select
Bits[3:1] set the mode of the fast detect output bits according to
Table 17.
Bit 0—Fast Detect Enable
Bit 0 is used to enable the fast detect output pins. When the FD
outputs are disabled, the outputs go into a high impedance state.
In LVDS mode when the outputs are interleaved, the outputs go
high-Z only if both channels are turned off (power-down/
standby/output disabled). If only one channel is turned off
(power-down/standby/output disabled), the fast detect outputs
repeat the data of the active channel.
Coarse Upper Threshold (Register 0x105)
Bits[7:3]—Reserved
Bits[2:0]—Coarse Upper Threshold
These bits set the level required to assert the coarse upper
threshold indication (see Table 21).
Fine Upper Threshold (Register 0x106 and Register 0x107)
Register 0x107, Bits[7:5]—Reserved
Register 0x107, Bits[4:0]—Fine Upper Threshold Bits[12:8]
Register 0x106, Bits[7:0]—Fine Upper Threshold Bits[7:0]
These registers provide a fine upper limit threshold. The 13-bit
value is compared with the 13-bit magnitude from the ADC
block and, if the ADC magnitude exceeds this threshold value,
the F_UT indicator is set.
Fine Lower Threshold (Register 0x108 and Register 0x109)
Register 0x109, Bits[7:5]—Reserved
Register 0x109, Bits[4:0]—Fine Lower Threshold Bits[12:8]
Register 0x108, Bits[7:0]—Fine Lower Threshold Bits[7:0]
These registers provide a fine lower limit threshold. This 13-bit
value is compared with the 13-bit magnitude from the ADC
block and, if the ADC magnitude is less than this threshold
value, the F_LT indicator is set.
Increase Gain Dwell Time (Register 0x10A and
Register 0x10B)
Register 0x10B, Bits[7:0]—Increase Gain Dwell Time
Bits[15:8]
Register 0x10A, Bits[7:0]—Increase Gain Dwell Time
Bits[7:0]
These register values set the minimum time in ADC sample
clock cycles (after clock divider) that a signal needs to stay below
the fine lower threshold limit before the F_LT and IG are
asserted high.
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Signal Monitor DC Correction Control (Register 0x10C)
Bit 7—Reserved
Bit 6—DC Correction Freeze
When Bit 6 is set high, the dc correction is no longer updated to
the signal monitor block, which holds the last dc value
calculated.
Bits[5:2]—DC Correction Bandwidth
Bits[5:2] set the averaging time of the signal monitor dc correction
function. This 4-bit word sets the bandwidth of the correction
block, according to the following equation:
where:
k is the 4 bit value programmed in Bits[5:2] of Register 0x10C
(values between 0 and 13 are valid for k; programming 14 or 15
provides the same result as programming 13).
f
Bit 1—DC Correction for Signal Path Enable
Setting this bit high causes the output of the dc measurement
block to be summed with the data in the signal path to remove
the dc offset from the signal path.
Bit 0—DC Correction for Signal Monitor Enable
This bit enables the dc correction function in the signal monitor
block. The dc correction is an averaging function that can be
used by the signal monitor to remove dc offset in the signal.
Removing this dc from the measurement allows a more
accurate power reading.
Signal Monitor DC Value Channel A (Register 0x10D and
Register 0x10E)
Register 0x10E, Bits[7:6]—Reserved
Register 0x10E, Bits[5:0]—DC Value Channel A[13:8]
Register 0x10D, Bits[7:0]—DC Value Channel A[7:0]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel A.
Signal Monitor DC Value Channel B (Register 0x10F and
Register 0x110)
Register 0x110, Bits[7:6]—Reserved
Register 0x110, Bits[5:0]—Channel B DC Value Bits[13:8]
Register 0x10F, Bits[7:0]—Channel B DC Value Bits [7:0]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel B.
Signal Monitor SPORT Control (Register 0x111)
Bit 7—Reserved
Bit 6—RMS/MS Magnitude Output Enable
Bit 6 enables the 20-bit rms or ms magnitude measurement as
output on the SPORT.
CLK
is the AD6653 ADC sample rate in hertz (Hz).
DC
_
Corr
_
BW
=
2
−
k
−
14
×
2
f
CLK
×
π