AD6653-150EBZ Analog Devices Inc, AD6653-150EBZ Datasheet - Page 46

• Manufacturer Part Number: AD6653-150EBZ
• Manufacturer: Analog Devices Inc

Specifications of AD6653-150EBZ

• Lead Free Status / Rohs Status: Compliant

AD6653
Addr.
(Hex)
0x0D
0x10
0x14
0x16
0x17
0x18
Digital Feature Control Registers
0x100
0x101
0x102
0x103
0x104
Register
Name
Test Mode
(Local)
Offset
Adjust
(Local)
Output Mode
Clock Phase
Control
(Global)
DCO Output
Delay
(Global)
VREF Select
(Global)
Sync Control
(Global)
f
Mix Control
(Global)
FIR Filter
and Output
Mode
Control
(Global)
Digital Filter
Control
(Global)
Fast Detect
Control
(Local)
S
/8 Output
Open
Open
Drive
strength
0 V to 3.3 V
CMOS or
ANSI
LVDS
1 V to 1.8 V
CMOS or
reduced
LVDS
(global)
Invert
DCO clock
Open
Signal
monitor
sync
enable
Open
Open
Open
Open
Bit 7
(MSB)
Reference voltage
00 = 1.25 V p-p
10 = 1.75 V p-p
01 = 1.5 V p-p
11 = 2.0 V p-p
(default)
selection
Bit 6
Open
Open
Output
type
0 = CMOS
1 = LVDS
(global)
Open
Open
Half-band
next sync
only
Open
Open
Open
Open
Bit 5
Open
Open
Reset
PN long
sequence
Offset adjust in LSBs from +31 to −32 (twos complement format)
Interleaved
CMOS
(global)
Open
Open
Half-band
sync
enable
Open
Open
f
S
/8 start state
Bit 4
Reset
PN short
sequence
Output
enable
bar
(local)
Open
Open
NCO32
next
sync only
Open
Open
Open
Rev. 0 | Page 46 of 80
Open
Open
Bit 3
Open
Open
NCO32
sync
enable
Open
FIR gain
0 = gain of
2
1 = gain of
1
Half-band
decimation
phase
(delay = 2500 ps × register value/31)
Fast Detect Mode Select[2:0]
DCO clock delay
00000 = 0 ps
00001 = 81 ps
11110 = 2419 ps
00010 = 161 ps
…
11111 = 2500 ps
Bit 2
Output
invert
(local)
Open
Clock
divider next
sync only
Open
f
mix disable
Spectral
reversal
S
/8 output
Input clock divider phase adjust
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating
101 = PN long sequence
110 = PN short sequence
111 = one/zero word toggle
Bit 1
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
Open
Clock
divider
sync
enable
f
sync only
Complex
output
enable
High-pass/
low-pass
select
S
/8 next
checkerboard
Bit 0
(LSB)
Open
Master
sync
enable
f
enable
FIR filter
enable
Open
Fast
detect
enable
S
/8 sync
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0xC0
0x00
0x00
0x00
0x01
0x00
Default
Notes/
Comments
When
enabled, the
test data is
placed on
the output
pins
in place of
ADC output
data
Configures
the outputs
and the
format of
the data
Allows
selection of
clock delays
into the
input clock
divider