AD6653-150EBZ Analog Devices Inc, AD6653-150EBZ Datasheet - Page 4

• Manufacturer Part Number: AD6653-150EBZ
• Manufacturer: Analog Devices Inc

Specifications of AD6653-150EBZ

• Lead Free Status / Rohs Status: Compliant

AD6653
GENERAL DESCRIPTION
The AD6653 is a mixed-signal intermediate frequency (IF) receiver
consisting of dual, 12-bit, 125 MSPS/150 MSPS ADCs and a wide-
band digital downconverter (DDC). The AD6653 is designed to
support communications applications where low cost, small size,
and versatility are desired.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compen-
sate for variations in the ADC clock duty cycle, allowing the
converters to maintain excellent performance.
ADC data outputs are internally connected directly to the
digital downconverter (DDC) of the receiver, simplifying layout
and reducing interconnection parasitics. The digital receiver has
two channels and provides processing flexibility. Each receive
channel has four cascaded signal processing stages: a 32-bit
frequency translator (numerically controlled oscillator (NCO)),
a decimating half-band filter, a fixed FIR filter, and an f
fixed-frequency NCO.
In addition to the receiver, DDC, the AD6653 has several functions
that simplify the automatic gain control (AGC) function in the
system receiver. The fast detect feature allows fast overrange
detection by outputting four bits of input level information with
short latency.
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In addition, the programmable threshold detector allows
monitoring of the incoming signal power using the four fast
detect bits of the ADC with low latency. If the input signal level
exceeds the programmable threshold, the coarse upper threshold
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition.
The second AGC-related function is the signal monitor. This block
allows the user to monitor the composite magnitude of the
incoming signal, which aids in setting the gain to optimize the
dynamic range of the overall system.
After digital processing, data can be routed directly to the two
external 12-bit output ports. These outputs can be set from 1.8 V
to 3.3 V CMOS or as 1.8 V LVDS. The CMOS data can also be
output in an interleaved configuration at a double data rate,
using only Port A.
The AD6653 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of the main
channel and the diversity channel. This IF sampling architecture
greatly reduces component cost and complexity compared with
traditional analog techniques or less integrated digital methods.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-bit
SPI-compatible serial interface.
The AD6653 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.