AD6653-150EBZ Analog Devices Inc, AD6653-150EBZ Datasheet - Page 13

• Manufacturer Part Number: AD6653-150EBZ
• Manufacturer: Analog Devices Inc

Specifications of AD6653-150EBZ

• Lead Free Status / Rohs Status: Compliant

ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
ELECTRICAL
ENVIRONMENTAL
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AVDD, DVDD to AGND
DRVDD to DRGND
AGND to DRGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
CML to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to DRGND
SDIO/DCS to DRGND
SMI SDO/OEB to DRGND
SMI SCLK/PDWN to DRGND
SMI SDFS to DRGND
DCOA/DCOB to DRGND
Operating Temperature Range
Maximum Junction Temperature
Storage Temperature Range
D0A/D0B through D11A/D11B
FD0A/FD0B through FD3A/FD3B
(Ambient)
Under Bias
(Ambient)
to DRGND
to DRGND
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +125°C
Rev. 0 | Page 13 of 80
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints and maximizes
the thermal capability of the package.
Table 7. Thermal Resistance
Package
Type
64-Lead LFCSP
1
2
3
4
Typical θ
plane. As shown, airflow increases heat dissipation, which
reduces θ
package leads from metal traces, through holes, ground, and
power planes, reduces the θ
ESD CAUTION
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
Per JEDEC JESD51-8 (still air).
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
9 mm × 9 mm
(CP-64-3)
JA
JA
. In addition, metal in direct contact with the
is specified for a 4-layer PCB with a solid ground
Airflow
Velocity
(m/s)
0
1.0
2.0
JA
.
θ
18.8
16.5
15.8
JA
1, 2
θ
0.6
JC
1, 3
θ
6.0
JB
AD6653
1, 4
Unit
°C/W
°C/W
°C/W