IS43LR32160B-6BLI ISSI, Integrated Silicon Solution Inc, IS43LR32160B-6BLI Datasheet - Page 11

• Manufacturer Part Number: IS43LR32160B-6BLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43LR32160B-6BLI

• Lead Free Status / Rohs Status: Compliant

Rev.00B | Dec. 2010
Mode Register
burst length, a burst type, a CAS latency. The mode register is programmed via the LOAD MODE REGISTER command and will retain the
stored information until programmed again, the device goes into deep power-down mode, or the device loses power.
and A7-A12 should be set to zero. BA0 and BA1 must be zero to access the mode register.
operation. Violating either of these requirements will result in unspecified operation.
Burst Length
(Mode Register Set Definition). The burst length determines the maximum number of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4, 8 or 16 are available for both the sequential and the interleaved burst types.
command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 when the burst
length is set to two; by A2-A8 when the burst length is set to four; by A3-A8 when the burst length is set to eight; and by A4-A8 when the
burst length is set to sixteen. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block.
The programmed burst length applies to both READ and WRITE bursts.
CAS Latency
data. The latency can be set to 2, 3 clocks, as shown in Figure (Standard Mode Register Definition).
For CL = 3, if the READ command is registered at clock edge n, then the data will be available at (n + 2 clocks + tAC). For CL = 2, if the
READ command is registered at clock edge n, then the data will be available at (n + 1 clock + tAC).
The mode register is used to define the specific mode of operation of the Mobile DDR SDRAM. This definition includes the selection of a
Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency,
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent
Figure7 : CAS Latency (BL=4)
Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
Command
/C K
C K
DQS
DQS
DQ
DQ
L
L
READ
T0
1tCK
Don ’t care
CL=2
NOP
2tCK
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T1
tRPRE
CL=3
tAC
T1n
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D
NOP
T2
OUT
n
tRPRE
tAC
D
n+1
T2n
OUT
D
D
IS43LR32160B, IS46LR32160B
n+2
NOP
T3
OUT
OUT
n
tRPST
D
D
n+3
n+1
T3n
OUT
OUT
D
n+2
NOP
T4
OUT
tRPST
D
Advanced Information
T4n
n+3
OUT
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