IS43LR32160B-6BLI ISSI, Integrated Silicon Solution Inc, IS43LR32160B-6BLI Datasheet - Page 25

• Manufacturer Part Number: IS43LR32160B-6BLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43LR32160B-6BLI

• Lead Free Status / Rohs Status: Compliant

Rev.00B | Dec. 2010
Note :
1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the
2. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to
3. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
4. Input slew rate.
5. These parameters guarantee device timing but they are not necessarily tested on each device.
6. The transition time for address and command inputs is measured between VIH and VIL.
7. A CK,/CK slew rate must be ≥ 1.0V/ns (2.0V/ns if measured differentially) is assumed for this parameter.
8. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
9. Input/Output Delta Rise/Fall Rate Derating
The value 1/slew rate(1) – 1/slew rate (2) (ns/V) determines the Δrise or Δfall rate and the adder for tDS or tDH.
10. A maximum of eight Refresh commands can be posted to any given Low-Power DDR SDRAM, meaning that the maximum absolute
11. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system.
12. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid
13. If either addend is not an integer, round up.
14. At least one clock pulse is required during t
15. The specifications in the table for T
clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to
reduce the data rate.
VIL(AC) for falling input signals.
through the DC region must be monotonic.
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
interval between any Refresh command and the next Refresh command is 8*tREFI.
It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or
transitioning from HIGH to LOW at this time, depending on tDQSS.
supports operation with T
CK,/CK setup/hold slew rate [V/ns]
Input setup/hold slew rate [V/ns]
I/O ∆ Rise or Fall Rate (ns/V)
±0.25
±0.50
1.0
0.8
0.6
1.0
0
A
> +85
°
C, and these values must be further constrained with T
REF
and T
∆tDS/∆tIS [ps]
∆tDS [ps]
+100
+50
∆tIS [ps]
XP
0
REFI
.
+100
+50
0
0
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are applicable for all temperature grades with T
∆tDH [ps]
+100
+50
∆tDH/∆tIH [ps]
0
∆tIH [ps]
- [e-mail]
+100
+50
0
0
IS43LR32160B, IS46LR32160B
∆tDS [ps]
+150
+75
REF
0
max of 32ms, and T
A
≤ +85°C. Only A2 temperature grade
∆tDH [ps]
+150
+75
Advanced Information
0
REFI
max of 3.9μs.
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