MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 32

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Getting Started
3.4.1
3.5
32
Table 1.
Note: A secondary video card accessed via the backplane is not supported in multiprocessing
Intel NetStructure
I/O Address Map (Sheet 2 of 2)
Analog Video Interface
The ZT 5524 / MPCBL5524 provides access to video at the faceplate through J10, using the Chips
and Technologies 69000 HiQVideo Accelerator with Integrated Memory, a 2 MB SDRAM video
device. Video connector J10 is a 15-pin subminiature D connector. Connector locations and pinouts
are documented in
The ZT 5524 / MPCBL5524 must be used with an analog monitor. If your monitor is capable of
both digital and analog modes, be sure it is set to analog.
Monitor timing specifications for supporting various display modes are provided in the 69000
HiQVideo Accelerator with Integrated Memory data sheet. A link to the datasheet for this device is
available in
The ZT 5524 / MPCBL5524 can be used in a wide variety of video applications. To ensure the best
quality display, take into account such factors as environment, noise from surrounding equipment,
video mode, distance from video source, and cabling.
The analog video signals are comprised of a horizontal and vertical sync and three color signals
(red, green, and blue). The signals are driven by a RAMDAC, which is used to convert the digital
video data to analog signals. The RAMDAC’s analog outputs have an impedance of 75 Ω . Ideally,
the connection to this output should use high-quality 75 Ω shielded cable.
environments when running under Windows 2000.
Video BIOS
The video BIOS provides low-level control of the VGA controller. It is used to interpret higher-
level commands and transform them into register-level instructions that the VGA controller can
understand. The ZT 5524 / MPCBL5524’s BIOS is fully IBM VGA and VESA compatible. The
BIOS is automatically installed during system initialization and is mapped to the standard
C0000 to C7FFFh VGA BIOS memory space.
Appendix E, “Video.”
®
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Appendix A, “ZT 5524 / MPCBL5524
40 - 43h
20 - 21h
0 - 1Fh
70h
61h
60h
NMI Enable Register
NMI Status Register
Positively Decoded, Passed to ISA
On-board Timer/Counters
On-board Master Interrupt Controller
On-board Master DMA Controller
Connectors.”.