MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 48

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Watchdog Timer
6.2
6.3
6.4
6.4.1
6.4.1.1
48
Intel NetStructure
Power-Up Initialization
The Watchdog Timer’s programmable logic is initialized only at power-up. This ensures that the
NMI, RST, NMI ENABLE, and RESET ENABLE status and control bits power up to unasserted
states, allowing the BIOS or user applications to determine the reset source (watchdog time-out,
power-up, power out-of-range/low voltage, and so on).
Time-Out Values
The watchdog timer has its own separate slow clock source. This clock runs at a maximum
frequency of 32 Hz (25 Hz nominal—because this slow clock is based on an RC oscillator, the
nominal timeout period is approximately 30% longer than the minimum value). The watchdog is
guaranteed to time-out in no less than the programmed minimum value.
Using the Watchdog in an Application
The following topics help you learn how to use the watchdog in an application. They describe the
watchdog’s reset and NMI functions and provide sample code. Watchdog reset and NMI are
controlled through the watchdog’s Control and Status register (referred to in this document as the
Watchdog register, Port 79h). See
Watchdog Reset
An application using the reset feature:
Enabling the Watchdog Reset
C code for enabling the watchdog reset might look like the following:
#define WD_RESET_EN_BIT_SET
void EnableWatchdogReset(void){
unsigned char WdValue;
WdValue = inb(WD_CSR_IO_ADDRESS);
WdValue |= WD_RESET_EN_BIT_SET;
local
outb(WD_CSR_IO_ADDRESS,WdValue);
// register.
}
1. Enables the watchdog reset
2. Sets the terminal count period
3. Periodically strobes the watchdog to keep it from resetting the system
4. If a strobe is missed, the watchdog assumes that an application error has occurred and resets
the system hardware
®
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Appendix B, “Watchdog (79h)”
0x20
// Holds watchdog register values.
//
// Read the current contents of the
//watchdog register.
// Assert the enable bit in the
//copy.
// Assert the enable in the watchdog
B for more information.