MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 75

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

B.1.3
Intel NetStructure
Table 35. Watchdog Bit Descriptions (Sheet 2 of 2)
Table 36. BIOS POST Codes Bit Description
BIOS POST Codes (80h)
I/O Address
Default Value
Size
Attribute
4
3
2:0
7:0
Bit
®
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Stage 1 Enable
Enables NMI activation on timeout.
Read Value:
0= Disabled
1= Enable NMI activation on timeout
Write Value:
0= Disable NMI operation of the watchdog. When the watchdog times out, the Stage 1 Monitor bit is
not set to 1 and the NMI output is not asserted
1= Enable NMI operation of the watchdog. When and if the watchdog times out:
The Stage 1 output (NMI) occurs after the period of time specified by the Terminal Count bits
The Stage 1 Monitor bit is set to 1 and stays high until set to 0 by software
The Stage 2 Reset occurs approximately 250 ms after Stage 1 output, allowing the system software to
take action before the reset occurs
Power-Up Value: 0
Post Time-Out Value: 0
A hard reset sets this bit to 0.
NMI or INIT steering
Terminal Count (TermCnt2…TermCnt0)
Read Value: Reflects the value written to bits 2 through 0
Write Value: These bits determine the terminal count of the watchdog
The minimum timeout period is given. The watchdog times out in no less than the minimum value.
The nominal timeout period is 30% longer than the minimum:
000 = 250 ms
001 = 500 ms
010 = 1 s
011 = 8 s
Power-Up Value: 000
A hard reset sets this bit to 000.
D7-D0. These bits correspond to eight green LEDs (labeled D0 through D7) on the bottom side of the
PCB. The Port 80 bits report the BIOS POST (diagnostic) codes. These LEDs may not be visible if a
“hot-swap shield” is installed on the bottom side on the PCB.
80h
0x00
8 bits
WO
100 = 32 s
101 = 64 s
110 = 128 s
111 = 256 s
Description
System Registers
75