MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 74

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

System Registers
74
Table 35. Watchdog Bit Descriptions (Sheet 1 of 2)
Intel NetStructure
7
6
5
Bit
Stage 2 Monitor (Reset Monitor)
Monitors the second stage (Reset) timer status.
Read Value:
0= Watchdog has not timed out since power up or since this bit was last set to 0
1= Watchdog reset timeout has occurred since power up or since this bit was last set to 0
Write Value:
0= Sets this bit to 0
1= No effect
Power-Up Value: 0
A hard reset not caused by a watchdog timeout sets this bit to 0.
Stage 1 Monitor (NMI Monitor)
Monitors the first stage (NMI) timer status.
Read Value:
0= Watchdog has not timed out since power up or since this bit was last set to 0
1= Watchdog timed out and NMI output was asserted
Write Value:
0= Sets this bit to 0
1= No effect
Power-Up Value: 0
A hard reset sets this bit to 0.
Stage 2 Enable
Enables second stage (Reset) activation on timeout.
Read Value:
0= Reset activation on timeout disabled
1= Reset activation on timeout enabled
Write Value:
0= Reset operation of the watchdog is not enabled. When the watchdog times out, the Stage 2
Monitor bit is not set to 1 and the Reset output is not asserted
1= Reset operation of the watchdog is enabled. When and if the watchdog times out:
The Reset output asserts
The Stage 2 Monitor bit is set to 1 and stays high until set to 0 by software
Reset action occurs approximately 250 ms after NMI
Power-Up Value: 0
Value After Timeout: 0 (doesn’t re-arm)
A hard reset sets this bit to 0.
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ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Description