PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 15

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

Revision 1.19 – June 17, 2009
PCI Express Controller
There are two independent PCI Express interfaces compliant with PCI Express base specification 1.1. One
interface can be configured as one to four lanes while the other functions as one-lane only. Both can be Root or
Endpoint Ports. The single lane interface shares a High-Speed SERDES with the Serial ATA (SATA) interface.
Features include:
AMCC Proprietary
Preliminary Data Sheet
• Two independent PCI Express interfaces
• Compliant with PCI Express base specification 1.1
• Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)
• Power Management
• Supports one virtual channel (VC0) no Traffic Class (TC) filtering
• Maximum Payload block size 512 Bytes
• Supports up to 512 Bytes maximum Read request size
• Requests supported:
• Buffering in each PCI Express port for the following transaction types:
• Parity checking on each buffer
• Programmable Outbound Memory (POM) regions: 3 memory, 1 I/O, 1 message, 1 configuration, 1 internal
• Programmable Inbound Memory (PIM) regions: 4 memory, 1 I/O, 1 expansion ROM
• INTx Interrupts support (legacy PCI):
• MSI - Message Signaled Interrupts
register
– One 4 lanes
– One 1 lane
– 2.5 GB/sec full duplex per lane
– Applications compliant with MSI rules are limited to one Endpoint port per PPC460EX
– up to 4 (x4) or 2 (x1) posted outbound Write requests (memory and messages)
– up to 4 (x4) or 2 (x1) posted inbound Write requests
– up to 4 (x4) or 2 (x1) outbound Read requests outstanding on PCI Express
– up to 4 (x4) or 2 (x1) inbound Read requests outstanding on PCI Express
– Outbound I/O request as a PCI Express Root Port
– Inbound I/O request as a PCI Express Endpoint
– 2KB Replay buffer: up to 4 in flight transactions
– 2KB (x4) or 1KB (x1) for Outbound posted Writes
– 2KB (x4) or 1KB (x1) for Outbound Reads completion
– 2KB (x4) or 1KB (x1) for Inbound posted Writes
– 2KB (x4) or 1KB (x1) for Inbound Reads completion
– Up to four INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC
– A/B/C/D INTx types generation for Endpoints
– MSI generation for Endpoint
– MSI termination for Root Ports
– MSI_X termination for Root Ports
460EX – PPC460EX Embedded Processor
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