PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 91

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

Revision 1.19 – June 17, 2009
The DDR SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed.
Note: MemClkOut can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR
The signals are terminated as indicated in Figure 8 for the DDR timing data in the following sections.
Programmable Timing
When initializing the DDR controller at boot time, calibration of various programmable delays is required. The
following parameters are programmable:
Board Layout Recommendations
The paths (traces) for the data and the associated data strobe signal should be routed with the same length
between PPC460EX and the SDRAM devices, allowing the rising and falling edges of the strobe to arrive at the
capture logic at the same time the data is in transition. Board designs must meet of the following criteria:
For example, traces that average 3.00 in. and 167ps/in., and meet the maximum 50ps skew requirement, have a
maximum length difference of 0.3in. and are between 2.85in. and 3.15in.
Clocking
Clocking skew to all DRAMs must be minimized. The maximum recommended flight-time skew between clocks for
different memory chips is 10ps. Because of the stringent requirements on DDR device clock inputs, it is expected
that board designers use some type of external PLL suitable to redrive the clock to the DDR SDRAMs when more
than two memory clocks are needed.. In such a system, the PLL acts as a zero-delay insertion buffer.
The PPC460EX (PPC460GT) has two identical memory clocks, MemClkOut0:1, eliminating the need to redrive the
memory clock for some board designs. Designs using a single registered DIMM or a single rank of directly attached
32-bit memory (2 x16 memory chips) does not require redriven clocks.
Feedback Signal
There are two options for handling the trace between the feedback driver and receiver, MemDCFbdkD to
MemDCFbdkR.
1. The feedback trace can be length matched to the round-trip delay measured from the rising edge of
AMCC Proprietary
DDR2/1 SDRAM Interface Specifications
Preliminary Data Sheet
• The internal delay of the DQS signals on a read is programmable. A single programmable delay globally
• The internal delay of the feedback signal on a read is programmable. The DDR controller drives and receives a
• The phase between the internal PLB clock and MemClkOut is programmable.
• The phase between the MemClkOut and the write DM, DQS, and data signals is programmable.
• Skew between the signals within any byte lane (8 DQ, 1 DQS, and 1 DM) should not exceed 50ps.
MemClkOut0:1 to the resulting input DQS on a read operation. Matching the feedback trace to the round-trip
delay, however, can negatively affect the sample cycle used by the DDR controller during reads. For this
reason, matching the trace length is not recommended for typical applications. Even when trace lengths are
matched to the round trip delay, software calibration of the feedback delay is still required.
affects all of the DQS signals.
pulse at the beginning of each read burst. The feedback pulse is driven and received by MemDCFbdkD and
MemDCFbdkR. This pulse is used to adjust the sample cycle.
programming register. In a typical system, users advance MemClkOut by 90 ° . This depends on the specific
application and requires a thorough understanding of the memory system in general (refer to the DDR
SDRAM Controller chapter in the PowerPC 460EX/EXr/GT Embedded Processor User’s Manual).
460EX – PPC460EX Embedded Processor
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