LFE3-150EA-8FN1156C Lattice, LFE3-150EA-8FN1156C Datasheet - Page 72

• Manufacturer Part Number: LFE3-150EA-8FN1156C
• Description: IC FPGA 149K LUTS 586I/O FN1156
• Manufacturer: Lattice
• Series: ECP3r

Specifications of LFE3-150EA-8FN1156C

• Number Of Logic Elements/cells: 149000
• Number Of Labs/clbs: 18625
• Total Ram Bits: 7014400
• Number Of I /o: 586
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeECP3 External Switching Characteristics (Continued)
f
Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using DLL -
CLKIN Pin for Clock Input
Data Left, Right and Top Sides and Clock Left and Right Sides
t
t
f
Generic DDRX1 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_RX.DQS.Centered) Using DQS
Pin for Clock Input
t
t
f
Generic DDRX1 Inputs with Clock and Data (<10bits wide) Aligned at Pin (GDDRX1_RX.DQS.Aligned) Using DQS Pin
for Clock Input
Data and Clock Left and Right Sides
t
t
f
Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX2_RX.ECLK.Centered) Using
PCLK Pin for Clock Input
Left and Right Sides
t
t
f
t
t
f
t
t
f
t
t
f
Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX2_RX.ECLK.Aligned)
Left and Right Side Using DLLCLKIN Pin for Clock Input
t
t
f
t
t
f
t
t
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
SUGDDR
HOGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
Parameter
DDRX1 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX1 Clock Frequency
Data Setup After CLK
Data Hold After CLK
DDRX1 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX1 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
Over Recommended Commercial Operating Conditions
Description
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices 0.775
All ECP3EA Devices
All ECP3EA Devices 535
All ECP3EA Devices 535
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices 0.775
All ECP3EA Devices
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
3-19
Device
DC and Switching Characteristics
0.775
0.775
0.790
Min. Max. Min. Max. Min. Max.
321
321
321
321
335
335
335
335
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LatticeECP3 Family Data Sheet
-8
0.225
0.225
0.225
0.225
0.210
250
250
250
250
405
405
405
405
460
460
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.775
0.775
0.775
0.775
0.790
535
535
403
403
403
403
425
425
425
425
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
0.225
0.225
0.225
0.225
0.210
1, 2
250
250
250
250
325
325
325
325
385
385
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.775
0.775
0.775
0.775
0.790
535
535
471
471
535
535
535
535
535
535
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
0.225
0.225
0.225
0.225
0.210
250
250
250
250
280
250
250
250
345
311
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
UI
UI
ps
ps
UI
UI
ps
ps
ps
ps
ps
ps
ps
ps
UI
UI
UI
UI
UI
UI