EPM240F100C5N Altera, EPM240F100C5N Datasheet - Page 26

• Manufacturer Part Number: EPM240F100C5N
• Description: IC MAX II CPLD 240 LE 100-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM240F100C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.7ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 240
• Family Name: MAX II
• # Macrocells: 192
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 24
• # I/os (max): 80
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1709

2–18
Figure 2–14. Global Clock Network
Notes to
(1) LAB column clocks in I/O block regions provide high fan-out output enable signals.
(2) LAB column clocks drive to the UFM block.
User Flash Memory Block
MAX II Device Handbook
I/O Block Region
LAB Column
Figure
clock[3..0]
2–14:
I/O Block Region
MAX II devices feature a single UFM block, which can be used like a serial EEPROM
for storing non-volatile information up to 8,192 bits. The UFM block connects to the
logic array through the MultiTrack interconnect, allowing any LE to interface to the
UFM block.
used to create customer interface or protocol logic to interface the UFM block data
outside of the device. The UFM block offers the following features:
■
■
■
■
4
Non-volatile storage up to 16-bit wide and 8,192 total bits
Two sectors for partitioned sector erase
Built-in internal oscillator that optionally drives logic array
Program, erase, and busy signals
4
(Note 1)
Figure 2–15
4
4
shows the UFM block and interface signals. The logic array is
4
CFM Block
UFM Block (2)
4
4
I/O Block Region
4
© October 2008 Altera Corporation
Chapter 2: MAX II Architecture
User Flash Memory Block
LAB Column
clock[3..0]