EPM240F100C5N Altera, EPM240F100C5N Datasheet - Page 45

• Manufacturer Part Number: EPM240F100C5N
• Description: IC MAX II CPLD 240 LE 100-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM240F100C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.7ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 240
• Family Name: MAX II
• # Macrocells: 192
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 24
• # I/os (max): 80
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1709

Chapter 3: JTAG and In-System Programmability
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Table 3–3. 32-Bit MAX II Device IDCODE (Part 2 of 2)
JTAG Block
© October 2008 Altera Corporation
EPM240Z
EPM570Z
Notes to
(1) The most significant bit (MSB) is on the left.
(2) The IDCODE’s least significant bit (LSB) is always 1.
Device
Table
f
f
3–2:
Version
(4 Bits)
0000
0000
For JTAG AC characteristics, refer to the
the MAX II Device Handbook.
For more information about JTAG BST, refer to the
Testing for MAX II Devices
The MAX II JTAG block feature allows you to access the JTAG TAP and state signals
when either the USER0 or USER1 instruction is issued to the JTAG TAP. The USER0
and USER1 instructions bring the JTAG boundary-scan chain (TDI) through the user
logic instead of the MAX II device’s boundary-scan cells. Each USER instruction
allows for one unique user-defined JTAG chain into the logic array.
Parallel Flash Loader
The JTAG block ability to interface JTAG to non-JTAG devices is ideal for general-
purpose flash memory devices (such as Intel- or Fujitsu-based devices) that require
programming during in-circuit test. The flash memory devices can be used for FPGA
configuration or be part of system memory. In many cases, the MAX II device is
already connected to these devices as the configuration control logic between the
FPGA and the flash device. Unlike ISP-capable CPLD devices, bulk flash devices do
not have JTAG TAP pins or connections. For small flash devices, it is common to use
the serial JTAG scan chain of a connected device to program the non-JTAG flash
device. This is slow and inefficient in most cases and impractical for large parallel
flash devices. Using the MAX II device’s JTAG block as a parallel flash loader, with
the Quartus II software, to program and verify flash contents provides a fast and cost-
effective means of in-circuit programming during test.
being used as a parallel flash loader.
0010 0000 1010 0101
0010 0000 1010 0110
Part Number
Binary IDCODE (32 Bits)
chapter in the MAX II Device Handbook.
000 0110 1110
000 0110 1110
Identity (11 Bits)
Manufacturer
(1)
DC and Switching Characteristics
IEEE 1149.1 (JTAG) Boundary-Scan
Figure 3–1
(1 Bit)
LSB
1
1
(2)
shows MAX II
MAX II Device Handbook
0x020A50DD
0x020A60DD
HEX IDCODE
chapter in
3–3