EPM240F100C5N Altera, EPM240F100C5N Datasheet - Page 30

• Manufacturer Part Number: EPM240F100C5N
• Description: IC MAX II CPLD 240 LE 100-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM240F100C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.7ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 240
• Family Name: MAX II
• # Macrocells: 192
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 24
• # I/os (max): 80
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1709

2–22
Figure 2–17. EPM570, EPM1270, and EPM2210 UFM Block LAB Row Interface
MultiVolt Core
Figure 2–18. MultiVolt Core Feature in MAX II Devices
MAX II Device Handbook
3.3-V or 2.5-V on
VCCINT Pins
The MAX II architecture supports the MultiVolt core feature, which allows MAX II
devices to support multiple V
regulator provides the necessary 1.8-V internal voltage supply to the device. The
voltage regulator supports 3.3-V or 2.5-V supplies on its inputs to supply the 1.8-V
internal voltage to the device, as shown in
guaranteed for voltages that are between the maximum recommended 2.5-V
operating voltage and the minimum recommended 3.3-V operating voltage.
The MAX IIG and MAX IIZ devices use external 1.8-V supply. The 1.8-V V
supply powers the device core directly.
1.8-V Core
Regulator
Voltage
Voltage
MAX II Device
CFM Block
UFM Block
RTP_BUSY
PROGRAM
DRDSHFT
OSC_ENA
CC
DRDCLK
ARSHFT
DRDout
ERASE
ARCLK
levels on the V
DRDin
ARDin
BUSY
OSC
VCCINT Pins
1.8-V on
Figure
CCINT
2–18. The voltage regulator is not
1.8-V Core
LAB
LAB
LAB
MAX IIG or MAX IIZ Device
Voltage
supply. An internal linear voltage
© October 2008 Altera Corporation
Chapter 2: MAX II Architecture
CC
MultiVolt Core
external