EPM240F100C5N Altera, EPM240F100C5N Datasheet - Page 32

• Manufacturer Part Number: EPM240F100C5N
• Description: IC MAX II CPLD 240 LE 100-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM240F100C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.7ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 240
• Family Name: MAX II
• # Macrocells: 192
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 24
• # I/os (max): 80
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1709

2–24
Figure 2–19. MAX II IOE Structure
Note to
(1) Available in EPM1270 and EPM2210 devices only.
I/O Blocks
MAX II Device Handbook
Figure
Data_in
2–19:
Fast_out
The IOEs are located in I/O blocks around the periphery of the MAX II device. There
are up to seven IOEs per row I/O block (5 maximum in the EPM240 device) and up to
four IOEs per column I/O block. Each column or row I/O block interfaces with its
adjacent LAB and MultiTrack interconnect to distribute signals throughout the device.
The row I/O blocks drive row, column, or DirectLink interconnects. The column I/O
blocks drive column interconnects.
Data_out
OE
Drive Strength Control
Programmable
Input Delay
Open-Drain Output
DEV_OE
Slew Control
Optional Schmitt
Trigger Input
Optional
PCI Clamp (1)
V
CCIO
V
CCIO
I/O Pin
Programmable
Pull-Up
© October 2008 Altera Corporation
Optional Bus-Hold
Circuit
Chapter 2: MAX II Architecture
I/O Structure